ASIC Physical Design, Principal Engineer

Synopsys; Sunnyvale (CA); On-site; USD 190,000 - 270,000; Full time

Job summary

Synopsys, Inc. seeks an experienced engineer to own physical integration for high-speed SerDes IP (56G/112G/224G PAM4/6) from floorplanning to GDSII. You will drive timing closure, power optimization, and signoff at 16nm and below, coordinating with front-end, analog, and CAD teams to assure robust tapeouts.

You will lead customer engagements on SOC-level integration planning, build and improve constraints and flows, mentor teammates, and help shape next-generation SerDes architectures.

Qualifications

• 10+ years in digital or physical SerDes design.
• Deep RTL-to-GDSII experience and chip-level integration.
• Experience with FinFET nodes (16nm or below) and low-power techniques.
• Strong scripting skills in Perl, Tcl, Python.

Responsibilities

• Own physical integration for advanced SerDes IP from floorplanning through GDSII.
• Drive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 across FinFET nodes.
• Develop timing constraints, clock architectures, and low-power design techniques.
• Lead customer engagements on physical integration topics, including tapeout support.
• Build and improve design methodologies, automation scripts, and flows that reduce customer effort.
• Debug and resolve complex analog-digital interface issues in collaboration with analog design and verification teams.
• Mentor engineers across the team on physical design best practices.

Skills

Digital/physical design

Timing closure

FinFET node knowledge

Scripting: Perl, Tcl, Python

Customer communication

Education

MSEE with 10+ years

BSEE with 12+ years

Tools

Perl

Tcl

Python

RTL-to-GDSII flow

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent over a decade taking SerDes and high-speed interface IP from RTL to silicon, and you know that the hardest problems are not the ones in the datasheet. They are the ones that show up at 16nm when your timing closure strategy collides with a power domain you did not account for, or when a customer integration uncovers an assumption you made six months ago that no longer holds. You are the engineer who catches those problems early, not because you are paranoid, but because you have seen what happens when they slip through.

You think in terms of flows, not just tasks. You know how to write the constraints that actually work, not just pass checks. You have debugged analog-digital interfaces enough times to respect the boundary and know when to pull in the right person instead of guessing. You can talk architecture with front-end teams, timing with CAD, and integration pain points with a customer who is three weeks from tapeout and needs a real answer, not a workaround.

At Synopsys, you will work on 112G and 224G PAM4/6 SerDes IP at nodes where every decision about placement, clocking, and power matters. The team is technical, the problems are real, and what you build will ship in products that move data at scale.

What You'll Be Doing

• Own physical integration for advanced SerDes IP from floorplanning through GDSII, including timing closure, power optimization, and signoff at 16nm and below
• Drive RTL-to-GDSII flows for 56G, 112G, and 224G PAM4/6 SerDes across FinFET nodes, working closely with front-end, analog, and CAD teams to resolve integration challenges
• Develop and validate timing constraints, clock architectures, and low-power design techniques that meet customer PPA targets and enable first-pass silicon success
• Lead customer engagements on physical integration topics, including SOC-level integration planning, constraint delivery, and tapeout support
• Build and improve design methodologies, automation scripts (Perl, Tcl, Python), and flows that reduce customer effort and improve delivery predictability
• Debug and resolve complex analog-digital interface issues in collaboration with analog design and verification teams
• Mentor engineers across the team on physical design best practices, timing closure strategies, and advanced node challenges

The Impact You Will Have

• Your physical integration work will enable high-speed SerDes IP to meet aggressive PPA targets in customer SoCs across data center, AI, and networking applications
• You will reduce customer integration effort and risk by delivering robust constraints, proven flows, and clear guidance that accelerates their tapeout schedules
• Your methodology improvements and automation will make the entire team faster and more consistent, reducing rework and late-stage surprises
• You will help shape the technical direction of future SerDes products by identifying architectural and flow improvements based on real tapeout learnings
• Your customer interactions will surface integration challenges early, allowing the team to address them in IP rather than forcing workarounds downstream
• You will build technical depth across the team by sharing what you have learned from advanced node tapeouts and complex mixed-signal integration
• Your work will directly contribute to the success of Synopsys SerDes IP in the most demanding, highest-performance applications in the industry

What You'll Need

• MSEE with 10+ years or BSEE with 12+ years of digital or physical design experience, with recent contributions to project tapeouts
• Deep hands-on experience with the full RTL-to-GDSII flow, including chip-level integration, timing closure, and physical signoff
• Proven experience with advanced FinFET nodes (TSMC 16nm or below), including low-power design techniques and process-specific challenges
• Strong understanding of timing constraint development, clock architecture, and design techniques required to meet power and area targets
• Experience leading technical initiatives or projects, with a track record of driving decisions and delivering results on schedule
• Solid understanding of digital and mixed-signal verification flows, SOC integration challenges, and analog-digital interface considerations
• Strong scripting and automation skills in Perl, Tcl, or Python, with a methodology-driven approach to design and CAD flows

Who You Are

• You can walk into a customer meeting three weeks before tapeout, understand their integration issue in fifteen minutes, and give them a path forward that actually works
• You make decisions with incomplete information because you know waiting for perfect clarity is not an option, and you are comfortable owning the call
• You know when a timing problem is a constraint problem, a floorplan problem, or an architecture problem, and you do not waste time solving the wrong one
• You push back when a plan does not make sense, whether it is a schedule, a methodology, or a customer request that will create more problems than it solves
• You can explain a complex physical design tradeoff to an analog engineer, a front-end architect, and a customer program manager, and have all three understand what matters to them
• You are comfortable with international travel when customer engagements or team collaboration require it

The Team You'll Be Part Of

You will be part of the Enterprise SerDes IP team, a group responsible for delivering high-speed interface IP across 56G, 112G, and 224G standards. The team works closely with front-end design, analog engineering, CAD, and product teams, as well as directly with customers on integration and tapeout support. Your work will involve collaboration across multiple internal functional groups and regular interaction with both internal and external customers.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.