Senior SerDes Design & Validation Engineer

Apple Inc.; Austin (TX); On-site; USD 185,000 - 325,000; Full time

Job summary

Apple is seeking a SerDes Design and Validation Engineer to lead system validation of mixed-signal SerDes IP. You will design, integrate and validate high-speed analog/MMS circuits for PHY applications, including receivers, transmitters, bias generators, clock generation and distribution networks.

You will develop test plans, perform data analysis, and drive lab and production tests with ATE systems. The role demands strong fundamentals, curiosity and leadership within a collaborative team.

Qualifications

• BS degree and at least 10 years in hardware/SerDes field.
• Proven expertise in high-speed SerDes IP validation and system bring-up.
• Experience with analog/mixed-signal circuits, DFT and lab testing.
• Strong debugging, data analysis and collaborative skills.

Responsibilities

• Own SerDes system bring-up, validation and debug in system environments.
• Define DFT needs to improve testability and silicon success.
• Collaborate with design and production-test teams.
• Lead lab evaluations and data-driven design improvements.

Skills

SerDes design

Mixed-signal design

DFT/testability

Lab automation

Scripting

Test and validation

PCIe/DP/USB MPHY familiarity

CDR architectures

Education

BS degree

Job description

Apple is seeking a SerDes Design and Validation Engineer to lead system validation of mixed-signal SerDes IP. You will design, integrate and validate high-speed analog/MMS circuits for PHY applications, including receivers, transmitters, bias generators, clock generation and distribution networks.

You will develop test plans, perform data analysis, and drive lab and production tests with ATE systems. The role demands strong fundamentals, curiosity and leadership within a collaborative team.