Lead SerDes Design & Validation for High-Speed IP

Apple Inc.; Cupertino, Northern (CA, KY); Hybrid; USD 185,000 - 325,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Apple stock programs

Tuition reimbursement

Relocation assistance

Performance bonuses

Job summary

Apple Inc. is seeking a SerDes Design and Validation Engineer to lead system validation of high-speed SerDes IP in Cupertino, CA.

You will own bring-up, validation, and debug of analog/digital blocks, define DFT needs, and work with design teams to ensure robust silicon for PCIe, USB, DP and MPHY interfaces. The role requires a strong background in analog/mixed-signal circuits, high-speed links, and lab-based testing with cross-functional collaboration across production validation teams.

Qualifications

• BS in Electrical Engineering with minimum 10 years of industry experience.
• Experience in high-speed SerDes, PCIe/USB/DP/MPHY protocols, and analog/mixed-signal design.
• Ability to lead SerDes system bring-up, validation, and debug; develop test plans and analyze data.

Responsibilities

• Ownership of SerDes system bring-up, validation and debug in system environment.
• Define DFT needs with design teams to improve testability and silicon yield.
• Involved in mixed-signal verification to understand SerDes operation and interaction with control logic.
• Develop and review test plans; collaborate with production test teams and diagnose bring-up issues.

Skills

SerDes design

System validation

High-speed serial links

Analog/mixed-signal design

DFT & test automation

Lab debugging

Scripting & automation

Firmware-assisted IP development

AI/ML concepts for silicon

Education

BS in Electrical Engineering

Tools

Bench testing

Job description

Apple Inc. is seeking a SerDes Design and Validation Engineer to lead system validation of high-speed SerDes IP in Cupertino, CA.

You will own bring-up, validation, and debug of analog/digital blocks, define DFT needs, and work with design teams to ensure robust silicon for PCIe, USB, DP and MPHY interfaces. The role requires a strong background in analog/mixed-signal circuits, high-speed links, and lab-based testing with cross-functional collaboration across production validation teams.