High-Speed SerDes & Analog IC Design Intern

Upscale, Inc.

Headquarters (WA)

On-site

USD 28,000 - 39,000

Part time

2 days ago
Be an early applicant

Get a reply from this employer

Your resume and cover letter, tailored to exactly what they’re hiring for.

Get past ATS filters

Job summary

Upscale, Inc. is seeking highly motivated summer interns to work with our engineering team on advanced SerDes and analog/mixed-signal IC design for AI infrastructure and data centers.

You will explore high-speed ADC design, foundation IP development, AI-driven circuit design, and ultra-low-jitter PLL modeling. This internship offers hands-on opportunities across architecture, simulation, and silicon measurement activities with a fast-moving team.

Qualifications

  • Strong fundamentals in analog and mixed-signal design, communication systems or related areas.
  • Proficiency in Python, MATLAB, or similar tools for modeling and data analysis.
  • Experience with circuit simulation, numerical analysis, or engineering computation.
  • Ability to independently investigate technical challenges and present results.

Responsibilities

  • Collaborate with engineers to investigate circuit and system-level design problems.
  • Develop analytical, behavioral, and circuit-level simulations to evaluate architectures.
  • Build scripts to automate simulation, data analysis, and design workflows.
  • Explore new algorithms and circuit techniques to improve performance and efficiency.
  • Present findings and design recommendations to the team.

Skills

Electrical engineering fundamentals
Python / MATLAB modeling
Circuit simulation experience
Analytical problem-solving
Independent research

Education

MS or PhD in Electrical Engineering, Computer Engineering, or related field

Job description

Upscale, Inc. is seeking highly motivated summer interns to work with our engineering team on advanced SerDes and analog/mixed-signal IC design for AI infrastructure and data centers.

You will explore high-speed ADC design, foundation IP development, AI-driven circuit design, and ultra-low-jitter PLL modeling. This internship offers hands-on opportunities across architecture, simulation, and silicon measurement activities with a fast-moving team.

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Advanced SerDes & Analog/Mixed-Signal IC Design Intern – Summer 2027
Advanced SerDes & Analog/Mixed-Signal IC Design Intern – Summer 2027

Upscale, Inc. • Headquarters (WA)

On-site
USD 28,000 - 39,000
Senior SerDes & ADC Architect (5nm, 100+ GS/s)
Senior SerDes & ADC Architect (5nm, 100+ GS/s)

Upscale, Inc. • United States

On-site
USD 335,000 - 388,000
Signal Integrity Engineer I - High-Speed AI Infrastructure
Signal Integrity Engineer I - High-Speed AI Infrastructure

Upscale, Inc. • United States

On-site
USD 117,000 - 129,000
Senior Signal Integrity Engineer — High-Speed AI & Networking
Senior Signal Integrity Engineer — High-Speed AI & Networking

Upscale, Inc. • United States

On-site
USD 159,000 - 170,000
Senior Distinguished Engineer, SerDes Receiver & ADC
Senior Distinguished Engineer, SerDes Receiver & ADC

Upscale, Inc. • United States

On-site
USD 335,000 - 388,000
Senior Director of SerDes Engineering: Build 100G+ IP
Senior Director of SerDes Engineering: Build 100G+ IP

Upscale, Inc. • United States

On-site
USD 306,000 - 337,000
Senior Director, High-Speed SerDes Layout
Senior Director, High-Speed SerDes Layout

Upscale, Inc. • United States

On-site
USD 306,000 - 337,000
Principal Analog Design Engineer — High-Speed AI SerDes
Principal Analog Design Engineer — High-Speed AI SerDes

Astera Labs • Irvine (CA)

On-site
USD 170,000 - 210,000
Discretionary bonus
Competitive benefits
Senior Signal Integrity Engineer — High-Speed AI
Senior Signal Integrity Engineer — High-Speed AI

Upscale, Inc. • Kentucky

On-site
USD 159,000 - 170,000
SerDes Design Intern (Analog/Mixed-Signal)
SerDes Design Intern (Analog/Mixed-Signal)

AMD • Santa Clara (CA)

Hybrid
USD 34,000 - 55,000