Senior SerDes & 100+ GS/s ADC Architect

Upscale; Kentucky; On-site; USD 180,000 - 260,000; Full time

Job summary

Upscale, Inc. is building world-class SerDes infrastructure for AI data centers and HPC, seeking a technical leader to define architecture for ultra-high-speed receivers and ADCs at 5nm and below.

You will guide analog front-end development, drive architectural trade-offs, and mentor engineers across DSP, clocking, digital, and silicon validation to deliver industry-leading SerDes performance.

Qualifications

• MS or PhD in Electrical Engineering or a related field, with extensive relevant experience in high-speed analog and mixed-signal IC design.
• Demonstrated expertise in high-speed SerDes receiver architecture and circuit implementation, including ADC-based receivers.
• Significant experience designing advanced CMOS circuits in 5nm or below process technologies.
• Strong hands-on understanding of high-speed ADC architectures and their practical implementation challenges.

Responsibilities

• Define and drive the architecture of next-generation, ultra-high-speed SerDes receivers, including the analog front end, ADC, sampling architecture, clocking interfaces, and integration with digital signal processing.
• Lead the design and optimization of ADCs targeting 100+ GS/s, addressing sampling speed, resolution, linearity, noise, power efficiency, and implementation complexity.
• Drive receiver front-end development, including high-bandwidth input stages, equalization, gain control, sampling networks, and other critical analog building blocks.
• Lead circuit design and implementation in 5nm and below technologies, leveraging advanced CMOS capabilities while managing device limitations and layout-dependent effects.
• Establish architectural trade-offs across bandwidth, SNR, ENOB, jitter tolerance, and power consumption to optimize overall link performance.
• Collaborate on clock generation and distribution, sampling-clock quality, aperture jitter, phase noise, and clock-to-data timing.

Skills

High-speed SerDes

Analog front-end design

Clocking and sampling

Education

MS or PhD in Electrical Engineering

Job description

Upscale, Inc. is building world-class SerDes infrastructure for AI data centers and HPC, seeking a technical leader to define architecture for ultra-high-speed receivers and ADCs at 5nm and below.

You will guide analog front-end development, drive architectural trade-offs, and mentor engineers across DSP, clocking, digital, and silicon validation to deliver industry-leading SerDes performance.