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Job summary
A technology firm in Elgin, Texas, is seeking a Verification Engineer to lead RTL design verification for high-speed digital systems. The role involves developing verification plans, building verification environments, and ensuring full test coverage while collaborating with design and architecture teams. Ideal candidates should have over 5 years of experience in digital engineering with a strong focus on verification and proficiency in SystemVerilog and UVM. Competitive compensation of $160,000 - $180,000 is offered.
Qualifications
5+ years in digital/RTL engineering.
3+ years in design verification.
Strong knowledge of VLSI verification flows.
Experience with SystemVerilog and UVM.
Responsibilities
Develop and execute verification plans based on design specs.
Build and maintain SV/UVM environments.
Define and close functional and code coverage.
Debug RTL and support regression testing.
Participate in reviews, test planning, and sign-off.
Skills
Digital/RTL engineering
Design verification
VLSI verification flows
SystemVerilog
UVM
Debugging
Problem-solving
Job description
A technology firm in Elgin, Texas, is seeking a Verification Engineer to lead RTL design verification for high-speed digital systems. The role involves developing verification plans, building verification environments, and ensuring full test coverage while collaborating with design and architecture teams. Ideal candidates should have over 5 years of experience in digital engineering with a strong focus on verification and proficiency in SystemVerilog and UVM. Competitive compensation of $160,000 - $180,000 is offered.