Senior RTL Integration Engineer for SoC Tapeouts

Acceler8 Talent; Mountain View (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A tech startup in Mountain View is looking for an experienced RTL Engineer to lead the top-level integration of complex SoCs. This role involves collaborating with various teams to ensure high-quality chip-level design and successful tapeouts. Ideal candidates will have expertise in SystemVerilog, strong integration experience, and the ability to handle diverse chip design concepts. This opportunity is crucial for advancing cutting-edge AI silicon production.

Qualifications

• Hands-on experience with top-level RTL integration of ASICs or SoCs.
• Strong skills in SystemVerilog for integration and debugging.
• Deep knowledge of chip-level design concepts.
• Experience with synthesis and sign-off flows.
• Proven track record of working across multi-disciplinary teams.

Responsibilities

• Own the top-level RTL integration of large, complex SoCs.
• Develop and maintain integration methodologies for scalable assembly.
• Drive chip-level reviews across milestones.
• Resolve integration issues with subsystem owners and verification teams.
• Deliver sign-off quality RTL suitable for synthesis and emulation.

Skills

Top-level RTL integration of ASICs or SoCs

SystemVerilog

Python

C/C++

Chip-level design concepts

Synthesis and sign-off flows

Job description

A tech startup in Mountain View is looking for an experienced RTL Engineer to lead the top-level integration of complex SoCs. This role involves collaborating with various teams to ensure high-quality chip-level design and successful tapeouts. Ideal candidates will have expertise in SystemVerilog, strong integration experience, and the ability to handle diverse chip design concepts. This opportunity is crucial for advancing cutting-edge AI silicon production.