Senior RTL Integration Engineer for SoC & DFT | Equity

NVIDIA; Austin (TX); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA's Advanced Technology Group is seeking a Full-Chip RTL Integration Engineer to join the FE-ASIC development team in Austin. You will lead RTL integration of multiple IPs into complex ASIC/SoC designs, owning clocking, reset architecture, and power-domain integration while ensuring design quality and verification readiness.

Collaborate with Architecture, Design, Verification, DFT and Physical Design to drive system-level integration, signoff, and smooth handoff across stages, with

Qualifications

• B.S./M.S. in Electrical/Computer Engineering or related field with 8+ years of ASIC/SoC RTL Integration experience.
• Strong SystemVerilog/UVM knowledge and hands-on verification experience.
• Experience with DFT methodologies (Scan, ATPG, MBIST, LBIST, JTAG) and signoff flows.

Responsibilities

• Lead RTL integration of multiple internal and third-party IPs into complex ASIC/SoC designs with top-level connectivity and clocking.
• Drive system-level integration, design closure, and cross-team collaboration with Architecture, RTL Design, Verification, DFT and Physical Design.
• Perform RTL quality checks (lint, CDC, RDC, synthesis) and develop integration verification plans using SystemVerilog/UVM.
• Collaborate with DFT teams to review ATPG/MBIST/LBIST results and ensure testability requirements.
• Support design signoff activities and handoff across implementation stages; develop automation to boost productivity.

Skills

RTL Integration

SystemVerilog

UVM

DFT methodologies

Debugging

Communication

Education

B.S./M.S. in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Siemens DFT tools

Job description

NVIDIA's Advanced Technology Group is seeking a Full-Chip RTL Integration Engineer to join the FE-ASIC development team in Austin. You will lead RTL integration of multiple IPs into complex ASIC/SoC designs, owning clocking, reset architecture, and power-domain integration while ensuring design quality and verification readiness.

Collaborate with Architecture, Design, Verification, DFT and Physical Design to drive system-level integration, signoff, and smooth handoff across stages, with