RTL Design Engineer (TERADYNE, North Reading, MA)

Teradyne; Reading (MA); On-site; USD 123,000 - 197,000; Full time

Benefits offered by this job

Health and well-being benefits

Medical, dental, vision coverage

Flexible Spending Accounts

Retirement savings plans

Life and disability insurance

Paid vacation & holidays

Tuition assistance

Job summary

Teradyne in North Reading, MA, seeks an experienced RTL Designer to join the Silicon Technology Engineering group. You will contribute to advanced node ASIC development, collaborating with Analog and architecture teams across specification, design, verification, physical design, and silicon bring-up.

The role emphasizes high-speed memory, timing closure, and automation via scripting. Minimum 5+ years in EE with Verilog RTL, CDC/STA, and memory/serial interfaces; strong collaboration with

Qualifications

• BSEE or MSEE in Electrical Engineering with 5+ years of experience.
• Extensive logic design experience writing RTL in Verilog.
• Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT.
• Experience with logic synthesis and timing constraints.
• Experience with clock domain crossings (CDC) and static timing analysis (STA).
• Experience with high speed memory and serial interfaces.
• Experience with automation through scripting such as Python, Tcl & Make.

Responsibilities

• Develop specifications, micro-architecture, and RTL design for mission-critical blocks with the chip architect.
• Integrate industry standard and Teradyne IPs.
• Collaborate with verification on test plans, debug, and coverage closure.
• Provide timing constraints and STA support to the Physical Design team through timing closure.
• Provide post-silicon lab bring-up and debug support.

Skills

Verilog RTL design

State machines & FIFOs

Synthesis & timing

CDC & STA

High-speed memory/serial

Scripting (Python/Tcl/Make)

Education

BSEE or MSEE in Electrical Engineering

Job description

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Date: Aug 10, 2026

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together,Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supportedto innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne’s products in many ways must be ahead of the semiconductor industry in order for our customers to ship production chips/products. You will join a best-in-class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup, and will have cutting-edge AI tools available to optimize your productivity.

Responsibilities:

• Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect
• Integration of industry standard and Teradyne custom IPs
• Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
• Providing timing constraints and STA support to the Physical Design team through timing closure
• Providing post silicon lab bringup and debug support

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BSEE or MSEE in Electrical Engineering or related field with 5+ years of experience.
• Extensive logic design experience writing RTL in Verilog
• Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT
• Experience with logic synthesis and timing constraints
• Experience with clock domain crossings (CDC) and static timing analysis (STA)
• Experience with high speed memory and serial
• Experience with automation through scripting such as Python, Tcl & Make

Compensation: The base salary range for this role is $123,100 - $196,900. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan:This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of comprehensive health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please clickhere to see details

We are an equal-opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.