RTL Design Engineer — Mixed-Signal ASICs & Bringup

LitePoint; North Reading (MA); On-site; USD 123,000 - 197,000; Full time

Job summary

Teradyne is seeking an experienced RTL Designer in the United States to join our Silicon Technology Engineering team. You will design RTL blocks in Verilog, work with chip architects, and coordinate with verification, physical design, and silicon bringup to ensure high-quality silicon.

The role requires a BSEE or MSEE and 5+ years of experience in logic design, with strong skills in Verilog, timing, and CDC/STA. On-site role with competitive base salary and discretionary bonuses.

Qualifications

• BSEE or MSEE in Electrical Engineering or related field.
• Extensive logic design experience writing RTL in Verilog.
• Experience with clock domain crossings and STA.

Responsibilities

• Develop specifications, micro-architecture, and RTL design of mission critical blocks.
• Integrate industry standard and Teradyne IPs.
• Collaborate with verification on test plans and coverage closure.
• Provide timing constraints and STA support to Physical Design.
• Provide post silicon lab bringup and debug support.

Skills

Verilog RTL coding

Logic design

Clock domain crossings

Python

Tcl

Make

Timing analysis

Education

BSEE or MSEE in Electrical Engineering

Tools

Python

Tcl

Make

Job description

Teradyne is seeking an experienced RTL Designer in the United States to join our Silicon Technology Engineering team. You will design RTL blocks in Verilog, work with chip architects, and coordinate with verification, physical design, and silicon bringup to ensure high-quality silicon.

The role requires a BSEE or MSEE and 5+ years of experience in logic design, with strong skills in Verilog, timing, and CDC/STA. On-site role with competitive base salary and discretionary bonuses.