Senior RTL Design & Verification Engineer (5+ yrs)

KellyOCG; Austin (TX); On-site; USD 88,000 - 120,000; Full time

Job summary

KellyOCG is seeking an RTL Design & Verification Engineer III to support the development and verification of complex semiconductor IP, including controllers, subsystems, and reusable IP components.

The ideal candidate has strong SystemVerilog experience and expertise in Formal Verification or UVM-based verification, with the ability to drive work from planning through verification closure, in a mostly onsite Austin, TX environment; 12-month W-2 contract with potential extension.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 5+ years of RTL design/verification experience.
• Strong SystemVerilog expertise.
• Experience with complex IP/SoC verification.
• Proficiency in simulation, lint, CDC/RDC, and verification methodologies.
• Expertise in Formal Verification or UVM-based verification.
• Cadence JasperGold experience is highly valued.
• Strong debugging and independent work skills.

Responsibilities

• Support development and verification of complex semiconductor IP, including controllers, subsystems, and reusable IP components.
• Drive work from planning through verification closure.

Skills

RTL design

Verification

SystemVerilog

Formal Verification

UVM Verification

Debugging

Independent work

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence JasperGold

Job description

KellyOCG is seeking an RTL Design & Verification Engineer III to support the development and verification of complex semiconductor IP, including controllers, subsystems, and reusable IP components.

The ideal candidate has strong SystemVerilog experience and expertise in Formal Verification or UVM-based verification, with the ability to drive work from planning through verification closure, in a mostly onsite Austin, TX environment; 12-month W-2 contract with potential extension.