RTL Design & Verification Engineer III

KellyOCG; Austin (TX); On-site; USD 88,000 - 120,000; Full time

Job summary

KellyOCG is seeking an RTL Design & Verification Engineer III to support the development and verification of complex semiconductor IP, including controllers, subsystems, and reusable IP components.

The ideal candidate has strong SystemVerilog experience and expertise in Formal Verification or UVM-based verification, with the ability to drive work from planning through verification closure, in a mostly onsite Austin, TX environment; 12-month W-2 contract with potential extension.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 5+ years of RTL design/verification experience.
• Strong SystemVerilog expertise.
• Experience with complex IP/SoC verification.
• Proficiency in simulation, lint, CDC/RDC, and verification methodologies.
• Expertise in Formal Verification or UVM-based verification.
• Cadence JasperGold experience is highly valued.
• Strong debugging and independent work skills.

Responsibilities

• Support development and verification of complex semiconductor IP, including controllers, subsystems, and reusable IP components.
• Drive work from planning through verification closure.

Skills

RTL design

Verification

SystemVerilog

Formal Verification

UVM Verification

Debugging

Independent work

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence JasperGold

Job description

Now Hiring: RTL Design & Verification Engineer III

Location: Austin, TX

Work Arrangement: Preferred onsite 4 days/week, but open to fully remote candidates within the U.S.

Contract: 12-month W-2 contract with potential for extension

Pay Rate: $75.50/hour

We are looking for an experienced RTL Design & Verification Engineer to support the development and verification of complex semiconductor IP, including controllers, subsystems, and reusable IP components.

The ideal candidate will have strong experience in SystemVerilog and either Formal Verification or UVM-based functional verification, along with the ability to independently drive work from planning through verification closure.

Key Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
• 5+ years of relevant industry experience
• Strong RTL design and/or verification experience
• Experience with complex IP, subsystems, or SoC environments
• Experience with simulation, lint, CDC, RDC, and verification methodologies
• Strong expertise in at least one of the following:
• Formal Verification, including assertions, property checking, model checking, equivalence checking, and proof convergence
• UVM Verification, including testbench development, constrained-random verification, coverage, assertions, scoreboards, and debug
• Hands-on experience with Cadence JasperGold is highly valued
• Strong debugging and problem-solving skills
• Ability to work independently and manage deliverables with minimal follow-up

Nice to Have

• Experience with both Formal Verification and UVM
• UPF / low-power design and verification
• APB, AHB, AXI, JTAG, scan, or fuse-programming interfaces
• Python, Perl, Tcl, or Shell scripting
• IP integration and SoC-level debug experience

Candidates with 5-10 years of focused, recent RTL design or verification experience are especially encouraged to apply.