Senior RTL Design Engineer - Verilog/SystemVerilog

Axiom Global Technologies; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Axiom Global Technologies seeks an experienced Logic RTL Design Engineer in Santa Clara to develop and integrate RTL blocks from system specifications. You will collaborate with Synthesis, STA, PD, DFT, and Verification teams to meet functional, performance, power, and area goals.

Responsibilities include creating RTL with Verilog/SystemVerilog/VHDL, performing static checks, and generating timing constraints, while supporting low-power design methods and advanced IP integrations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of hands-on Logic/RTL Design experience
• Strong fundamentals in VLSI design
• Strong proficiency in Verilog, SystemVerilog, and/or VHDL
• Experience with RTL coding, integration, synthesis, timing constraints, Lint, and CDC
• Strong problem-solving and analytical skills
• Ability to work effectively with cross-functional engineering teams

Responsibilities

• Develop hardware architecture and RTL designs based on system and block-level specifications
• Write and integrate RTL using Verilog, SystemVerilog, and/or VHDL
• Perform Lint, CDC, synthesis, LEC, and STA checks and debug issues identified during static analysis
• Develop timing constraint files and work closely with STA and Physical Design teams to address timing requirements
• Design and integrate top-level RTL, including clocks, resets, configuration registers, and IP blocks
• Develop and execute low-power design methodologies using UPF/CPF
• Support verification teams with functional debug and assist Physical Design teams with timing constraints and other design-related issues
• Collaborate with Synthesis, STA, PD, DFT, and Verification teams to achieve functional, performance, power, and area goals
• Develop and integrate advanced peripheral and interface IPs
• Support design activities involving JESD204C, including integration of third-party licensed IP and PHY components
• Apply DFT concepts and address functional issues introduced by DFT structures
• Take ownership of assigned tasks and drive them through successful completion
• Contribute to design methodologies, tools, flows, signoff, and optimization using a data-driven approach
• Collaborate effectively with distributed and remote engineering teams

Skills

RTL design

VLSI fundamentals

Verilog/SystemVerilog/VHDL

timing constraints

design verification

Synthesis

STA

Physical Design

DFT

Verification teams

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Design Compiler

SpyGlass

Cadence

Synopsys

LEC

STA

Job description

Axiom Global Technologies seeks an experienced Logic RTL Design Engineer in Santa Clara to develop and integrate RTL blocks from system specifications. You will collaborate with Synthesis, STA, PD, DFT, and Verification teams to meet functional, performance, power, and area goals.

Responsibilities include creating RTL with Verilog/SystemVerilog/VHDL, performing static checks, and generating timing constraints, while supporting low-power design methods and advanced IP integrations.