Senior RTL Design Engineer for SoC Timing & Power

Synopsys, Inc.; Gilbert, Northern (AZ, KY); Hybrid; USD 110,000 - 150,000; Full time

Job summary

Synopsys, Inc. in Gilbert, Arizona is seeking an RTL design engineer to translate RTL specifications into synthesizable Verilog/SystemVerilog and VHDL that meet timing and area constraints.

You will collaborate with verification and physical design teams to debug testbenches, close coverage gaps, and drive timing closure for real SoC designs used in automotive, aerospace, and compute applications. The role is hybrid in Gilbert, AZ, requiring clear communication across global teams and a focus on

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering.
• 3–4 years of hands-on ASIC/FPGA RTL design, implementation, and debugging.
• Strong Verilog, SystemVerilog or VHDL RTL coding for registers, pipelines, state machines, memories, and FIFOs.
• Experience with ASIC design flow from micro-architecture to RTL, synthesis, and timing closure.
• Familiarity with AXI, APB, AHB, I2C and SPI; knowledge of PCIe, DDR or Ethernet a plus.
• Verification scripting in Python or C++ and Git workflows preferred.

Responsibilities

• Write and review RTL for block designs based on micro-architecture specifications.
• Run RTL quality checks using linting, CDC/RDC analysis, and synthesis to ensure clean design before handoff to physical design.
• Collaborate with verification engineers to debug testbench failures, refine corner cases, and close coverage gaps.
• Work with physical design teams to resolve timing issues, optimize logic for synthesis, and support timing closure from netlist through signoff.
• Implement standard interface protocols including AXI, APB, AHB, I2C, and SPI within SoC subsystems.
• Use scripting in Python, Tcl, or shell to automate repetitive tasks in the design flow and improve team productivity.
• Participate in design reviews with cross-functional teams across the globe, clearly communicating design decisions and tradeoffs.

Skills

RTL design

Verilog/SystemVerilog

VHDL RTL

ASIC/FPGA RTL

Synthesis

Lint

CDC/RDC analysis

Python scripting

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Simulators

Lint checkers

Synthesis tools

Static timing analysis

Job description

Synopsys, Inc. in Gilbert, Arizona is seeking an RTL design engineer to translate RTL specifications into synthesizable Verilog/SystemVerilog and VHDL that meet timing and area constraints.

You will collaborate with verification and physical design teams to debug testbenches, close coverage gaps, and drive timing closure for real SoC designs used in automotive, aerospace, and compute applications. The role is hybrid in Gilbert, AZ, requiring clear communication across global teams and a focus on