Senior RTL Design Engineer - Ultra-Low-Power SoC & NoC

Efficient Computer; San Jose (CA); On-site; USD 180,000 - 245,000; Full time

Job summary

Efficient Computer seeks a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC, focusing on on-chip interconnect and memory interfaces, low-power logic, and peripheral IP. You will collaborate with architects, DV, physical design, and firmware to tape out a leading ultra-low-power fabric.

This unique role joins a growing HW engineering team moving from initial product development to market release and scaled production.

Qualifications

• 8–10 years of front-end digital design experience on processor, accelerator, or SoC.
• Significant contributions to at least two tapeout cycles.
• Strong proficiency in SystemVerilog for synthesizable RTL: state machines, arbiters, FIFOs and datapath logic.
• Hands-on experience with standard VLSI front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, isolation, and retention.
• Working knowledge of on-chip bus protocols (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL level.
• Experience with on-chip memories: SRAM wrappers, memory-mapped interfaces.

Responsibilities

• Design, integrate, and sign off RTL for compute fabric blocks, on-chip networks/NoC, memory interfaces and peripherals.
• Integrate third-party and in-house IP at the subsystem and SoC level, including bus fabric hookup.
• Write and maintain architecture and design documentation; present in design reviews.
• Run simulations, lint, CDC/RDC analysis, and ensure timing/area/power targets; support timing closure.
• Drive issues to closure with physical design during timing/congestion closure.

Skills

SystemVerilog

RTL design

Synthesis

Low-power design

Debugging

Tools

lint

CDC/RDC

LEC

STA

waveform tools

Job description

Efficient Computer seeks a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC, focusing on on-chip interconnect and memory interfaces, low-power logic, and peripheral IP. You will collaborate with architects, DV, physical design, and firmware to tape out a leading ultra-low-power fabric.

This unique role joins a growing HW engineering team moving from initial product development to market release and scaled production.