Lead Digital Design Engineer — Power-Efficient Edge SoC

Efficient Computer; San Jose (CA); On-site; USD 160,000 - 270,000; Full time

Benefits offered by this job

401K match

Equity program

Paid parental leave

Flexibility

Job summary

Efficient is seeking a Lead Digital Design Engineer to own microarchitecture definition and RTL implementation across the dataflow fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP integration. You will tape out an industry-leading power-efficient SoC and work with architects, DV leads, physical design, and firmware teams.

This is a unique opportunity to influence hardware from architecture to market release, shaping edge computing at scale with a

Qualifications

• 8+ years RTL design experience with tape-out ownership on a processor/accelerator SoC.
• Deep proficiency in SystemVerilog and synthesis-clean design.
• Experience with dataflow, memory subsystems, and on-chip interconnects.
• Experience with low-power RTL techniques and bus protocols.
• Ability to read SDC constraints and timing reports.

Responsibilities

• Own microarchitecture and RTL for dataflow compute units.
• Define on-chip interconnects, memory interfaces, and low-power design.
• Lead PPA reviews and collaborate across DV, physical design, and firmware.
• Mentor RTL engineers and drive design reviews.

Skills

RTL design

SystemVerilog

Dataflow arch

Memory subsystems

On-chip interconnect

Low-power RTL

Bus protocols

RTL verification

Tools

UPF flows

Synthesis tools

Timing analysis tools

Job description

Efficient is seeking a Lead Digital Design Engineer to own microarchitecture definition and RTL implementation across the dataflow fabric, memory subsystem, on-chip interconnect/NoC, low-power logic, and standard peripheral IP integration. You will tape out an industry-leading power-efficient SoC and work with architects, DV leads, physical design, and firmware teams.

This is a unique opportunity to influence hardware from architecture to market release, shaping edge computing at scale with a