Lead RTL Design Engineer for Energy-Efficient Dataflow SoC

Efficient Computer; Austin (TX); On-site; USD 200,000 - 275,000; Full time

Benefits offered by this job

Equity

401(k) match

Paid parental leave

Competitive benefits

Job summary

Efficient Computer in Austin, TX is building power-efficient edge and data-center compute with its Fabric architecture. The Lead RTL Design Engineer will own microarchitecture definition and RTL implementation across the dataflow fabric, memory subsystem, and NoC, driving performance, power and area targets while collaborating with architects, DV, and firmware teams.

The role offers ownership of architecture specs, tape-out readiness, and a path from initial product development to market

Qualifications

• 8+ years RTL design experience with tape-out ownership of dataflow based design or related SoC components.
• Deep proficiency in SystemVerilog for RTL - synthesis-clean and timing-aware.
• Experience with on-chip memory design and low-power RTL techniques.
• Familiarity with standard on-chip bus protocols at RTL level (AXI/TileLink).
• Strong ability to read SDC constraints and timing reports.

Responsibilities

• Own microarchitecture definition for processor and compute-unit blocks within the dataflow fabric.
• Define on-chip interconnects and system integration strategies.
• Define interfaces to memory subsystem and data movement behavior.
• Lead configuration/scheduling/execution of workloads on the fabric.
• Drive power architecture, clocking and power domains.

Skills

RTL design

SystemVerilog

Dataflow architecture

On-chip interconnect

Low-power RTL

Memory subsystem design

Synthesis & timing

Hardware/Software co-design

Tools

AXI

TileLink

NoC protocol

Job description

Efficient Computer in Austin, TX is building power-efficient edge and data-center compute with its Fabric architecture. The Lead RTL Design Engineer will own microarchitecture definition and RTL implementation across the dataflow fabric, memory subsystem, and NoC, driving performance, power and area targets while collaborating with architects, DV, and firmware teams.

The role offers ownership of architecture specs, tape-out readiness, and a path from initial product development to market