Senior RTL Design Engineer - ASIC, SystemVerilog & QoS

InterSources Inc; Saratoga (CA); On-site; USD 140,000 - 220,000; Full time

Job summary

InterSources Inc. is seeking a senior engineer with 8–15 years of ME/BE experience to design and optimize ASIC-related systems.

The role requires hands-on SystemVerilog/Verilog, in-depth knowledge of ASIC methodologies, and strong analytical skills for debugging complex networking issues. The candidate should be proficient in enabling high-performance scheduling and QoS mechanisms, with experience in Ethernet and IP protocols and a proven ability to communicate effectively within

Qualifications

• 8–15 years of ME/BE experience.
• Hands-on knowledge of SystemVerilog and Verilog is mandatory.
• Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
• Proven expertise in designing and optimizing scheduling and QoS mechanisms.
• Experience with Ethernet and IP protocols.
• Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
• Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

Skills

Analytical thinking

Problem solving

Communication skills

Team collaboration

Tools

SystemVerilog

Verilog

Ethernet

IP protocols

ASIC design methodologies

Scheduling QoS

Job description

InterSources Inc. is seeking a senior engineer with 8–15 years of ME/BE experience to design and optimize ASIC-related systems.

The role requires hands-on SystemVerilog/Verilog, in-depth knowledge of ASIC methodologies, and strong analytical skills for debugging complex networking issues. The candidate should be proficient in enabling high-performance scheduling and QoS mechanisms, with experience in Ethernet and IP protocols and a proven ability to communicate effectively within