Senior RTL IC Design Engineer – Onsite, Data Center AI/ML

Broadcom

San Jose (CA)

On-site

USD 144,000 - 230,000

Full time

7 days ago
Be an early applicant
Application generator

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Get past ATS filters

Benefits offered by this job

401(k) matching
Employee Stock Purchase Program (ESPP)
Paid holidays
Vacation time
Sick leave
Medical, dental & vision

Job summary

Broadcom is seeking a Digital IC Design Engineer in San Jose, CA to work in the Data Center Solutions Group on PCIe Switch products and data center infrastructure. You will implement RTL designs using Verilog/SystemVerilog and collaborate across Verification, Software, Emulation, and Validation teams.

The role requires a minimum of a Bachelor’s degree and 12+ years of relevant experience, with on-site work only. A strong background in RTL, timing closure and complex algorithms is essential.

Qualifications

  • Bachelor’s degree in Electrical/Electronics/Computer Science/Computer Engineering or equivalent engineering degree.
  • 12+ years of relevant industry experience.
  • In-depth knowledge of RTL design and Verilog/SystemVerilog.

Responsibilities

  • High-level architecture specification analysis.
  • Micro-architecture development and documentation.
  • RTL implementation and optimization for timing closure using Verilog/SystemVerilog.
  • RTL debugging and robust solutions.
  • Collaborate with Verification, Software/Firmware, Emulation and Validation teams.
  • Lab support for silicon during validation.
  • On-site work; no remote work.

Skills

RTL design
Verilog/SystemVerilog
Cross-functional teamwork

Education

Bachelor’s degree in EE/CS/CE

Job description

Broadcom is seeking a Digital IC Design Engineer in San Jose, CA to work in the Data Center Solutions Group on PCIe Switch products and data center infrastructure. You will implement RTL designs using Verilog/SystemVerilog and collaborate across Verification, Software, Emulation, and Validation teams.

The role requires a minimum of a Bachelor’s degree and 12+ years of relevant experience, with on-site work only. A strong background in RTL, timing closure and complex algorithms is essential.

Get your free, confidential resume review.

or drag and drop your file here.