Senior RTL/ASIC Design Engineer — Microarchitecture & IP

Socket.dev; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google in Mountain View is seeking an experienced hardware design engineer to help shape the next generation of custom silicon. You will define microarchitecture, integrate IP, and contribute to chip-level verification, delivering high performance and energy efficiency for our consumer products.

Candidates should have a bachelor’s degree in engineering or related field, 4 years IP development experience, and familiarity with Verilog/VHDL and scripting languages.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC design with Verilog or VHDL.
• Experience with a scripting language like Perl or Python.

Responsibilities

• Define microarchitecture for a subsystem.
• Integrate internal and/or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

IP development experience

Verilog/VHDL

Perl/Python scripting

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science or related field

Master's degree or PhD in EE/CE/CS (preferred)

Tools

Verilog

VHDL

Job description

Google in Mountain View is seeking an experienced hardware design engineer to help shape the next generation of custom silicon. You will define microarchitecture, integrate IP, and contribute to chip-level verification, delivering high performance and energy efficiency for our consumer products.

Candidates should have a bachelor’s degree in engineering or related field, 4 years IP development experience, and familiarity with Verilog/VHDL and scripting languages.