RTL Design Engineer, Silicon

Socket.dev; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google in Mountain View is seeking an experienced hardware design engineer to help shape the next generation of custom silicon. You will define microarchitecture, integrate IP, and contribute to chip-level verification, delivering high performance and energy efficiency for our consumer products.

Candidates should have a bachelor’s degree in engineering or related field, 4 years IP development experience, and familiarity with Verilog/VHDL and scripting languages.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC design with Verilog or VHDL.
• Experience with a scripting language like Perl or Python.

Responsibilities

• Define microarchitecture for a subsystem.
• Integrate internal and/or external IP.
• Define microarchitecture of a small to medium size IP.
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Skills

IP development experience

Verilog/VHDL

Perl/Python scripting

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science or related field

Master's degree or PhD in EE/CE/CS (preferred)

Tools

Verilog

VHDL

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with IP development or integration.
• Experience in ASIC development withVerilogor VHDL.
• Experience with a scripting language like Perl or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
• Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
• Knowledge of high-performance and energy efficient design techniques.
• Knowledge of FPGA and emulation platforms.
• Knowledge of ASIC Verification or DFT.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:

• Define microarchitecture for a subsystem.
  
• Integrate internal and/or external IP.
  
• Define microarchitecture of a small to medium size IP.
  
• Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
  
• Participate in test plan and coverage analysis of the sub-system and chip-level verification.