Senior CPU RTL Design Engineer — Cache & Microarchitecture

Google; Mountain View (CA); On-site; USD 163,000 - 237,000; Full time

Job summary

Google in Mountain View, CA, USA seeks a Senior CPU RTL Design Engineer to advance CPU cache subsystems with RTL focus. You will collaborate across performance, architecture, and software teams to evaluate trade-offs and optimize microarchitectures for future CPUs.

Requires a Bachelor's in a related field and 8 years' experience with SystemVerilog, Lint, UPF, and CPU cache designs. Google offers a strong compensation package and equity as part of total rewards.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 8 years of experience in implementation of CPU cache subsystems, including load-store unit or private/shared L2/L3 designs.
• Experience with RTL language (e.g. System Verilog) and related design processes (Lint, UPF).

Responsibilities

• Engage in developing CPU cache subsystems, focusing on RTL design and microarchitecture for future CPU generations.
• Collaborate with performance, architecture, and software teams to evaluate trade-offs and suggest microarchitectural improvements that boost performance.
• Deliver high-quality designs on time while articulating the advantages and disadvantages of various microarchitecture updates.
• Partner with verification, power, and physical design teams to ensure designs meet area, power, and frequency targets.
• Optimize cache unit design and coordinate with other design units within CPU subsystems to achieve excellent power, performance, and area.

Skills

RTL design

SystemVerilog

Lint

UPF

CPU cache subsystems

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Google in Mountain View, CA, USA seeks a Senior CPU RTL Design Engineer to advance CPU cache subsystems with RTL focus. You will collaborate across performance, architecture, and software teams to evaluate trade-offs and optimize microarchitectures for future CPUs.

Requires a Bachelor's in a related field and 8 years' experience with SystemVerilog, Lint, UPF, and CPU cache designs. Google offers a strong compensation package and equity as part of total rewards.