Senior CPU Emulation Engineer – FPGA & RTL Specialist

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google in Mountain View seeks a senior RTL/FPGA engineer to help shape the next generation of hardware for direct-to-consumer products. You will architect RTL partitioning, drive FPGA synthesis, and validate complex multi-block systems spanning emulation platforms.

You will collaborate with DV and silicon design teams, optimize model compile times, and define robust test suites and workloads for pre-silicon verification and system validation. Competitive compensation includes equity and benefits.

Qualifications

• Bachelor's degree or equivalent in EE/CS or related field.
• 8+ years with industry-standard emulation/FPGA prototyping platforms.
• Experience RTL design using Verilog/SystemVerilog; scripting in Python/Perl/TCL/Makefiles.

Responsibilities

• Architect and drive RTL partitioning for emulation platforms.
• Define and execute test suites and performance benchmarks for pre-silicon verification.
• Guide debugging methodologies across multi-million gate designs.
• Lead optimization of compile times and FPGA routing efficiency.
• Create automation workflows and collaborate with IP design/verification teams.

Skills

RTL design

Verilog / SystemVerilog

Scripting / automation

Education

Bachelor's degree or equivalent

Tools

ZeBu/HAPS

Palladium/Protium

Veloce

Job description

Google in Mountain View seeks a senior RTL/FPGA engineer to help shape the next generation of hardware for direct-to-consumer products. You will architect RTL partitioning, drive FPGA synthesis, and validate complex multi-block systems spanning emulation platforms.

You will collaborate with DV and silicon design teams, optimize model compile times, and define robust test suites and workloads for pre-silicon verification and system validation. Competitive compensation includes equity and benefits.