RTL Engineer

DensityAI; Mountain View (CA); On-site; USD 250,000 - 375,000; Full time

Benefits offered by this job

Equity grant

Medical / dental / vision

401(k)

PTO

Job summary

DensityAI is seeking a seasoned RTL design engineer to own the design of digital blocks for our AI accelerator. You will oversee microarchitecture, SystemVerilog implementation, and integration, translating architectural specs into synthesizable RTL that meets PPA targets.

You will collaborate with DV, PD, and DFT teams across the RTL2GDS flow to tape out silicon, while leveraging Python/Tcl for automation and tackling advanced interconnects and memory subsystems.

Qualifications

• 5+ years designing complex RTL blocks or SoCs to silicon.
• Strong Verilog/SystemVerilog RTL and microarchitecture skills.
• Experience with synthesis, timing, constraints (SDC/STA) and lint.
• Collaborates with DV, PD, and DFT across RTL2GDS flow to tapeout.
• Proficient in scripting for design automation (Python/Tcl).
• Knowledge of high-speed interfaces (HBM, PCIe, SerDes) is a plus.

Responsibilities

• Own RTL design of digital blocks/subsystems for the accelerator.
• Translate specs into efficient, synthesizable RTL meeting PPA targets.
• Drive microarchitecture tradeoffs for high performance and low power.
• Partner with DV, PD, and DFT across verification and timing flows.
• Ensure block-level quality: constraints, lint, CDC, and timing signoff.
• Contribute to architecture reviews and silicon bring-up delays.
• Develop and extend AI-assisted tool flows for design/verification.

Skills

RTL design

SystemVerilog

Microarchitecture

Synthesis/Timing

Python/Tcl scripting

DV/verification collaboration

Tools

HBM

PCIe

SerDes

Job description

About The Role

Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks - compute datapath, memory subsystem, on-chip interconnect, and control logic - from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon.

What You'll Do

• Own RTL design of digital blocks/subsystems for our accelerator - microarchitecture definition, SystemVerilog implementation, and integration
• Translate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targets
• Drive microarchitecture trade-offs - pipelining, datapath vs. control, clock/power gating - for high-performance, low-power design
• Partner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testability
• Own block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoff
• Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up
• Use and develop AI-assisted tool flows to accelerate design and verification

What We're Looking For

• Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL
• 5+ years designing complex digital blocks/SoCs taken to silicon
• Solid microarchitecture skills - pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoC
• Synthesis & timing awareness - writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lint
• Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout
• Scripting (Python/Tcl/) for design automation
• (Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototyping

Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.

Visa Sponsorship

DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.

Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Equal Opportunity

DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.

Full compensation packages are based on candidate experience and relevant certifications.

California pay range: $250,000 USD - $375,000 USD