AI Accelerator RTL Design Engineer — High-Performance SoCs

River AI; San Francisco (CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health benefits

Dental benefits

Vision benefits

Unlimited PTO

Relocation support

Job summary

River AI seeks exceptional RTL design engineers to architect and implement high-performance AI accelerator and related SoC components. You will own large parts of the chip, focusing on architecture, micro-architecture, and implementation, collaborating with compiler, verification, and physical design teams.

Role responsibilities include RTL development, physical design integration, and performance optimization.

Qualifications

• Bachelors in Electrical Engineering or Computer Engineering with 5+ years on advanced nodes (7nm or below).
• Strong hands-on RTL, synthesis, physical design, and timing tool experience (SystemVerilog, VCS/Verdi, Fusion Compiler, PrimeTime).
• Expert knowledge in computer architecture for SoCs/CPUs/GPUs/AI accelerators.
• Proven silicon delivery with ECOs at scale.
• Collaborative mindset to push boundaries with engineers.

Responsibilities

• Architecture & micro-architecture: define architecture for AI hardware subsystems.
• RTL Development: implement complex logic in SystemVerilog with high throughput and power-aware data paths.
• Physical Design Integration: work with backend for synthesis, floorplanning, STA to meet target frequencies.
• Performance Integration: partner with compiler and perf teams to identify bottlenecks across the stack.

Skills

RTL design

SystemVerilog

Chip architecture

Performance modeling

Collaboration

ECOs

Education

Bachelors in EE/CE

Tools

VCS/Verdi

Fusion Compiler

PrimeTime

Job description

River AI seeks exceptional RTL design engineers to architect and implement high-performance AI accelerator and related SoC components. You will own large parts of the chip, focusing on architecture, micro-architecture, and implementation, collaborating with compiler, verification, and physical design teams.

Role responsibilities include RTL development, physical design integration, and performance optimization.