Senior RTL Network Architect for AI Accelerators

Nicedesignjobs; San Francisco (CA); On-site; USD 210,000 - 270,000; Full time

Job summary

OpenAI is seeking a senior RTL engineer to own on-chip and off-chip communication components for a custom AI accelerator platform. You will drive microarchitecture, SystemVerilog implementation, verification, and silicon bring-up for high-bandwidth NoC fabrics and network interfaces.

The role requires hands-on leadership, collaboration with architecture and performance teams, and mentoring junior engineers to ensure production-ready silicon across complex interconnects.

Qualifications

• Proven hands-on RTL ownership for networking/datapath RTL.
• Experience with Verilog/SystemVerilog and production-quality RTL.
• Ability to drive microarchitecture through tape-out and silicon bring-up.

Responsibilities

• Own microarchitecture, RTL design, and delivery of interconnect and networking components (NoC fabrics, switches, routers).
• Develop on-chip/off-chip interfaces and custom networking protocols for scale-up/scale-out systems.
• Lead RTL design, simulation, verification, and debug; monitor latency, bandwidth, and utilization.

Skills

Verilog/SystemVerilog

RTL design

NoC fabrics

Networking protocols

SystemVerilog verification

Performance analysis

Architecture collaboration

RTL debugging

Job description

OpenAI is seeking a senior RTL engineer to own on-chip and off-chip communication components for a custom AI accelerator platform. You will drive microarchitecture, SystemVerilog implementation, verification, and silicon bring-up for high-bandwidth NoC fabrics and network interfaces.

The role requires hands-on leadership, collaboration with architecture and performance teams, and mentoring junior engineers to ensure production-ready silicon across complex interconnects.