Principal RTL Design Engineer for AI Accelerator

Doist; San Jose (CA); On-site; USD 180,000 - 255,000; Full time

Job summary

SambaNova Systems, based in the US, is seeking a Principal RTL Design Engineer to own microarchitecture and RTL for a major RDU block. You will drive hardware design from specification through tape-out, collaborating with architects, verification, and software teams to optimize timing, power, and area while mentoring others.

You will work with aggressive targets and contribute to advanced EDA flows, sharing responsibility for delivering high-performance AI accelerators.

Qualifications

• BS or MS in EE, CE, or CS with 7+ years of experience in ASIC RTL design.
• Mastery of synthesizable SystemVerilog for high-speed ASICs, including SVA.
• High-frequency design: datapath pipelining, retiming, timing targets.
• Deep foundation in computer architecture and digital logic design.
• Ownership of a complex block from spec through tape-out on production ASIC.
• Physical-design awareness: floorplan, congestion, timing feedback.
• Synthesis and static timing analysis, lint, CDC, LEC quality flows.
• Scripting in Python for design and flow automation.

Responsibilities

• Own microarchitecture and RTL implementation for a major block or subsystem of the RDU, from specification through tape-out
• Define and document microarchitecture specifications for complex digital blocks in compute, memory, or on-chip network subsystems
• Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
• Hit aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
• Own PPA for your area: make and defend the power, performance, and area trade-offs using advanced techniques for high-speed design
• Drive timing closure with physical design: synthesis, STA, critical-path iteration, and response to floorplan and congestion feedback
• Own design quality gates for your area: lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
• Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
• Work with architects and software teams to prototype and evaluate features that improve application-level performance
• Drive AI, automation, and new EDA tool methodologies into the design flow
• Set the technical bar in design reviews and mentor design engineers

Skills

SystemVerilog

Python scripting

Microarchitecture design

RTL design

SVA

Synthesis & STA

Leadership without authority

Education

BS in EE/CE/CS

MS in EE/CE/CS

Job description

SambaNova Systems, based in the US, is seeking a Principal RTL Design Engineer to own microarchitecture and RTL for a major RDU block. You will drive hardware design from specification through tape-out, collaborating with architects, verification, and software teams to optimize timing, power, and area while mentoring others.

You will work with aggressive targets and contribute to advanced EDA flows, sharing responsibility for delivering high-performance AI accelerators.