Senior RISC-V ISA Simulator Engineer

QUALCOMM, Inc.; Cupertino (CA); Hybrid; USD 176,000 - 263,000; Full time

Benefits offered by this job

Annual discretionary bonus

RSU grants

Comprehensive benefits

Job summary

Qualcomm Technologies, Inc. is seeking a Senior Software Engineer to implement a high-performance RISC-V Instruction Set Simulator (ISS) in C++ at the Cupertino, CA site.

You will contribute to a production-grade simulator that serves as a golden reference for 64-bit RISC-V processors, supporting verification flows, RTL co-simulation, and Linux boot testing. The role emphasizes correctness, performance, and a strong foundation in processor architecture, with exposure to low-level systems

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field with 4+ years of hardware/software experience
• Master's degree with 3+ years of hardware/software experience in related fields
• PhD with 2+ years of hardware/software experience in related fields

Responsibilities

• Translate RISC-V specification chapters into working C++ code.
• Maintain fetch/decode/execute engine, memory protection and privilege logic.
• Co-simulation with RTL; flag differences one instruction at a time.

Skills

C++

Processor architecture

Systems programming

Debugging

Python 3+

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science

Master's degree in Electrical Engineering, Computer Engineering, Computer Science

PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

QEMU

Spike

gem5

GDB

ELF binaries

Job description

Qualcomm Technologies, Inc. is seeking a Senior Software Engineer to implement a high-performance RISC-V Instruction Set Simulator (ISS) in C++ at the Cupertino, CA site.

You will contribute to a production-grade simulator that serves as a golden reference for 64-bit RISC-V processors, supporting verification flows, RTL co-simulation, and Linux boot testing. The role emphasizes correctness, performance, and a strong foundation in processor architecture, with exposure to low-level systems