Senior C++ Engineer for RISC-V ISS & Co-simulation

MaC VC; Cupertino (CA); On-site; USD 176,000 - 263,000; Full time

Job summary

Qualcomm Technologies, Inc. is hiring a software/verification engineer to build a high‑performance RISC‑V Instruction Set Simulator (ISS). You will translate the ISA into clean, correct C++ code and optimize it for long-running benchmarks and Linux boot.

The role sits at the intersection of architecture and systems software, with co-simulation against RTL, a focus on testing, and tooling that helps software teams debug pre‑silicon firmware efficiently.

Qualifications

• Translate RISC-V specification chapters into working C++ code.
• Maintain fetch/decode/execute engine, memory protection, virtual memory, and privilege-level logic.
• Co-simulation harness to run ISS alongside RTL, flag differences one instruction at a time.
• Write targeted unit tests to exercise features and compare against the RISC-V spec.

Responsibilities

• Implementing the ISA by translating RISC-V specs into C++.
• Ensure correctness and performance of the simulator on long-running benchmarks.
• Develop testing strategies and verification plans for new extensions.

Skills

C++ programming

Processor architecture

Systems programming

Debugging

Hardware verification

Education

Bachelor's degree in EE/CE/CS

Master's degree in EE/CE/CS

PhD in EE/CE/CS

Tools

QEMU

Spike

gem5

Job description

Qualcomm Technologies, Inc. is hiring a software/verification engineer to build a high‑performance RISC‑V Instruction Set Simulator (ISS). You will translate the ISA into clean, correct C++ code and optimize it for long-running benchmarks and Linux boot.

The role sits at the intersection of architecture and systems software, with co-simulation against RTL, a focus on testing, and tooling that helps software teams debug pre‑silicon firmware efficiently.