RISC-V ISS Engineer: High-Performance C++ Simulator

QUALCOMM, Inc.

Cupertino (CA)

Sur place

USD 176 000 - 263 000

Plein temps

14 jours+

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Résumé du poste

Qualcomm Technologies, Inc. is building a high-performance RISC-V Instruction Set Simulator (ISS) used as the golden reference model for next-generation 64-bit processors.

The role blends architecture, systems software, and verification engineering, demanding precise C++ that is correct to the bit and fast enough for long-running benchmarks. Responsibilities include translating the RISC-V spec into code, expanding ISA support, maintaining the core engine, and creating unit tests that verify

Qualifications

  • Strong C++ skills and ability to read unfamiliar codebases.
  • Comfortable with processor architecture concepts: pipelines, memory, privilege levels, interrupts.
  • Attention to detail; spec-driven; correctness matters.
  • Willingness to read specifications and turn into tested code.
  • Exposure to low-level or systems programming (embedded OS, compilers, hardware).

Responsabilités

  • Translate the RISC-V specification into working C++ code for 64-bit processors.
  • Implement diverse extensions: integer, floating point, vector, bit manipulation, security, interrupts.
  • Maintain fetch/decode/execute engine, memory protection, virtual memory, and privilege logic.
  • Develop tests and co-simulation harnesses with RTL to compare against reference results.

Connaissances

C++ mastery
Processor architecture
Specification reading
Low-level programming

Formation

Bachelor’s degree
Master’s degree

Outils

GDB
ELF binaries
Bare-metal bring-up

Description du poste

Qualcomm Technologies, Inc. is building a high-performance RISC-V Instruction Set Simulator (ISS) used as the golden reference model for next-generation 64-bit processors.

The role blends architecture, systems software, and verification engineering, demanding precise C++ that is correct to the bit and fast enough for long-running benchmarks. Responsibilities include translating the RISC-V spec into code, expanding ISA support, maintaining the core engine, and creating unit tests that verify

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