RFIC Layout Designer for High-Frequency RFICs

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

SpaceX is seeking a RFIC Layout Designer to lead the discipline of layout for analog and RFIC blocks, collaborating with systems architecture and verification teams. You will drive full-chip layout on multiple silicon projects for space and ground infrastructure, emphasizing power distribution, matching, and parasitic control.

The role requires strong analog layout skills, experience with 22nm+ nodes, and the ability to work with EDA tools and scripting.

Qualifications

• Strong analog layout skills
• Experience in advanced node IC layouts (22nm, 16nm, 7nm, 5nm or below)
• Experience in layout of RF blocks such as LNAs, VCOs and mixers
• Experience with skill programming
• Experience with shell scripting, Python or Perl
• Experience managing revision control systems
• Experience with circuit design
• Understanding layout considerations for device matching, coupling and noise isolation
• Working knowledge of Linux
• Excellent communication skills (oral and written)
• Able to work independently on challenging problems

Responsibilities

• Determine chip floor plan with IC designers and leads, including power/ground distribution and pad locations
• Estimate layout schedule and flag complex areas early
• Layout custom RF/analog circuit blocks with attention to matching and parasitics
• Perform DRC, ERC, LVS and resolve errors
• Integrate top-level layout with ESD structures and pad assembly; finalize tape-out and density fill
• Collaborate with EDA vendors to test new tools/features
• Create guides and demos to share layout techniques

Skills

Analog layout

RFIC layouts

Advanced node

RF blocks layout

Skill programming

Shell scripting

Python

Perl

Revision control

Circuit design

Device matching

Linux

Communication skills

Independence

Education

Bachelor’s degree in Electrical or Computer Engineering

Job description

SpaceX is seeking a RFIC Layout Designer to lead the discipline of layout for analog and RFIC blocks, collaborating with systems architecture and verification teams. You will drive full-chip layout on multiple silicon projects for space and ground infrastructure, emphasizing power distribution, matching, and parasitic control.

The role requires strong analog layout skills, experience with 22nm+ nodes, and the ability to work with EDA tools and scripting.