RFIC Layout Engineer - High-Frequency RF

InvestedintheMission; Irvine (CA); On-site; USD 105,000 - 170,000; Full time

Benefits offered by this job

Stock options

401(k) plan

Medical, vision & dental coverage

Paid time off & holidays

Job summary

SpaceX is seeking a RFIC Layout Designer to lead the discipline of layout for advanced RF/analog IC designs used in space and ground infrastructure. You will collaborate with cross‑disciplinary teams to deliver full-chip layouts with low parasitics and robust ESD/packaging integration.

The role requires a strong background in analog RF layout at advanced nodes (22nm/16nm/7nm/5nm or below), experience with Linux, scripting, and design verification processes, and the ability to work independently

Qualifications

• Bachelor’s degree in electrical or computer engineering or equivalent experience.
• 1+ years of professional IC layout design experience or 3+ years in lieu of a degree.

Responsibilities

• Determine chip floor plan including power/ground distribution and pad locations in collaboration with IC designers and packaging engineers.
• Estimate layout schedules and identify complex areas needing early investigation.
• Layout of custom RF and analog blocks with focus on matching and minimizing parasitics.
• Perform DRC/ERC and LVS checks and fix errors.
• Coordinate top-level layout with ESD structures, pad assemblies and tape-out readiness including density fill and manufacturability checks.

Skills

Strong analog layout

Advanced node IC layouts

RF/Analog circuit layout

Skill programming

Shell scripting

Python

Revision control systems

Circuit design experience

Linux knowledge

Excellent communication

Independent problem solving

Education

Bachelor’s degree in electrical or computer engineering

Tools

EDA tools

Job description

SpaceX is seeking a RFIC Layout Designer to lead the discipline of layout for advanced RF/analog IC designs used in space and ground infrastructure. You will collaborate with cross‑disciplinary teams to deliver full-chip layouts with low parasitics and robust ESD/packaging integration.

The role requires a strong background in analog RF layout at advanced nodes (22nm/16nm/7nm/5nm or below), experience with Linux, scripting, and design verification processes, and the ability to work independently