Senior RFIC Design Engineer — Satellite Communications

SpaceX; Redmond (WA); On-site; USD 165,000 - 270,000; Full time

Benefits offered by this job

Company stock

Long-term incentives

Medical, vision, dental

401(k)

Paid parental leave

Vacation and holidays

SpaceX shuttles for commuting

Job summary

SpaceX is seeking a motivated RFIC Design Engineer to join the RFIC engineering team in Redmond, WA. You will design, simulate, and model RF/analog/mixed-signal ICs for next-generation Starlink components, partnering with systems, firmware, and ASIC teams to optimize performance.

Responsibilities include floor planning, layout, characterization of prototypes, and collaboration with manufacturing on production testing.

Qualifications

• Bachelor's degree in EE/CE/CS.
• 5+ years of RF integrated circuit experience.

Responsibilities

• Design, simulate and model RF/analog/mixed-signal circuits and systems.
• Derive specifications for RFIC subsystems and circuits.
• Develop Analog/Mixed-Signal/RF/microwave circuits in SiGe or CMOS processes.
• Collaborate with system architects, modem/DSP and ASIC engineers to partition hardware/software.
• Perform IC floor planning and layout.
• Model package and external parasitic components.
• Evaluate and characterize prototypes of the design.
• Characterize and analyze full radio performance.
• Assist in developing automated test lab equipment for lab measurements.
• Work with manufacturing engineers on production testing and qualification of RFIC components and systems.

Skills

RFIC design

Circuit simulation

RF/microwave knowledge

Education

Bachelor's degree in electrical engineering, computer engineering, or computer science

Master's degree or PhD in electrical/computer engineering (RF/Analog focus)

Tools

Spectre

ADS

HFSS

Momentum

Job description

SpaceX is seeking a motivated RFIC Design Engineer to join the RFIC engineering team in Redmond, WA. You will design, simulate, and model RF/analog/mixed-signal ICs for next-generation Starlink components, partnering with systems, firmware, and ASIC teams to optimize performance.

Responsibilities include floor planning, layout, characterization of prototypes, and collaboration with manufacturing on production testing.