Senior STA & Sign-Off Engineer, High-Speed IP

Synopsys Inc; Sunnyvale (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

Synopsys Inc is seeking an experienced ASIC Digital Signoff Engineer in sunny California. As part of the IP Digital Design Methodology team, you will define ASIC design standards and collaborate globally on cutting-edge digital IP cores.

The ideal candidate will possess over 12 years of hands-on experience, particularly in Static Timing Analysis and EM/IR flows, showcasing strong problem-solving skills and technical documentation abilities. Join us to contribute to the next generation of technology.

Qualifications

• 12+ years of hands-on experience in CAD flows for high-speed digital IP cores and/or SOCs.
• Direct hands-on experience with advanced node STA/Timing signoff flows at SoC level.
• Knowledge of IP deliverables, ASIC implementation, and physical design flow.

Responsibilities

• Develop and deploy advanced node signoff methodologies for IP designs.
• Drive the best PPA for IP designs.
• Evaluate signoff timing, power, physical verification, and ECOs.

Skills

Static Timing Analysis (STA)

EM/IR Analysis

Cross-functional collaboration

Problem-solving skills

Education

BS or MS in Electrical Engineering

Tools

Synopsys tools

StarRC

ICV

Job description

Synopsys Inc is seeking an experienced ASIC Digital Signoff Engineer in sunny California. As part of the IP Digital Design Methodology team, you will define ASIC design standards and collaborate globally on cutting-edge digital IP cores.

The ideal candidate will possess over 12 years of hands-on experience, particularly in Static Timing Analysis and EM/IR flows, showcasing strong problem-solving skills and technical documentation abilities. Join us to contribute to the next generation of technology.