Senior Principal SerDes Analog/Mixed-Signal Engineer

Upscale; Kentucky; On-site; USD 120,000 - 180,000; Full time

Job summary

Upscale, Inc. is hiring an experienced analog/mixed-signal design engineer to lead high-speed SerDes development and IP blocks for AI workloads in Kentucky. You will translate system specs into circuit architectures, optimize performance, and drive design closure through silicon bring-up and characterization.

Ideal candidates have MS/PhD in EE with 100G+ experience, strong modeling skills in SPICE and modern tools, and proven ability to mentor engineers and collaborate across teams.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• Significant industry experience in analog/mixed-signal IC design (100G+).
• Proven transistor-level design, simulation, and performance optimization experience.
• Experience taking complex circuit blocks through implementation, verification, and design closure.

Responsibilities

• Own design and development of complex analog/mixed-signal circuits for high-speed SerDes and foundation IP.
• Translate system-level specifications into circuit architectures, design strategies, and measurable targets.
• Evaluate architectural alternatives and optimize performance, power, area, noise, linearity, bandwidth, and robustness.
• Lead transistor-level design, behavioral modeling, simulation, verification, and post-layout performance closure.
• Drive technical reviews, communicate trade-offs, and provide guidance to other engineers.
• Support silicon bring-up, characterization, correlation against simulations, and root-cause analysis of performance issues.

Skills

Analog/mixed-signal design

High-speed SerDes

Technical communication

Cross-functional collaboration

Education

M.S. or Ph.D. in Electrical Engineering

Tools

Spectre/SPICE

HSPICE

Python

MATLAB

Job description

Upscale, Inc. is hiring an experienced analog/mixed-signal design engineer to lead high-speed SerDes development and IP blocks for AI workloads in Kentucky. You will translate system specs into circuit architectures, optimize performance, and drive design closure through silicon bring-up and characterization.

Ideal candidates have MS/PhD in EE with 100G+ experience, strong modeling skills in SPICE and modern tools, and proven ability to mentor engineers and collaborate across teams.