Lead SerDes IC Design Engineer - High-Speed Analog/Mixed-Signal

Upscale, Inc.; Kentucky; On-site; USD 223,000 - 243,000; Full time

Job summary

Upscale AI is seeking analog and mixed-signal design engineers to develop SerDes circuits and foundation IP for high-bandwidth, energy-efficient AI infrastructure.

You will design, simulate, and optimize circuits, collaborate across architecture, digital, and layout teams, and contribute to silicon characterization and post-layout verification. Competitive compensation and equal opportunity.

Qualifications

• B.S., M.S., or Ph.D. in Electrical Engineering or related field.
• Experience in analog/mixed-signal IC design and high-speed circuits.
• Strong transistor-level circuit design and analog/mixed-signal simulation knowledge.
• Hands-on with SPICE-based simulators and IC design workflows.
• Scripting in Python or MATLAB.
• Strong analytical and teamwork skills.

Responsibilities

• Design, simulate, and optimize analog and mixed-signal circuits for SerDes and IP.
• Transistor-level design, modeling, and performance analysis.
• Develop testbenches, analyze behavior, troubleshoot issues.
• Collaborate with architecture, digital, physical design, layout, and validation teams.
• Participate in design reviews and mitigate risks.
• Support physical implementation, post-layout verification, characterization, and debugging.
• Develop scripts to improve simulation efficiency and data analysis.
• Document methodologies, results, and findings.

Skills

Analog/mixed-signal design

High-speed circuit design

Transistor-level design

Python scripting

Analog/mixed-signal simulation

Education

B.S., M.S., or Ph.D. in Electrical Engineering

Tools

SPICE-based simulators

CAD/EDA tools

Python

MATLAB

Job description

Upscale AI is seeking analog and mixed-signal design engineers to develop SerDes circuits and foundation IP for high-bandwidth, energy-efficient AI infrastructure.

You will design, simulate, and optimize circuits, collaborate across architecture, digital, and layout teams, and contribute to silicon characterization and post-layout verification. Competitive compensation and equal opportunity.