Senior Principal PCIe/CXL Verification Engineer

Cadence; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Benefits offered by this job

Bonus

Equity

401(k) match

Employee stock purchase plan

Medical dental and vision coverage

Job summary

Cadence is seeking an experienced engineer to advance PCIe AVIP and PCIe/CXL Virtual Bridge products. You will focus on protocol functionality, performance, and robustness across hardware and software boundaries.

The role involves feature bring‑up, validation, debugging BFMs and transactors, and delivering customer-ready solutions in a high‑impact R&D team. Familiarity with emulation platforms is a strong plus.

Qualifications

• Bachelor's degree with extensive experience in digital design and architecture.
• Strong understanding of interconnect protocols and verification flows.
• Experience with SystemVerilog/Verilog and software interfaces.

Responsibilities

• Design and implement protocol functionality for PCIe AVIP and Virtual Bridge components.
• Develop and debug BFMs, transactors, and software interfaces.
• Ensure performance, correctness, and scalability in emulation flows.
• Collaborate with cross-functional teams and support customer issues.

Skills

Digital design

Computer architecture

SystemVerilog/Verilog

C/C++

System-level verification

Education

BS with 10+ years experience

MS with 7+ years experience

PhD with 5+ years experience

Job description

Cadence is seeking an experienced engineer to advance PCIe AVIP and PCIe/CXL Virtual Bridge products. You will focus on protocol functionality, performance, and robustness across hardware and software boundaries.

The role involves feature bring‑up, validation, debugging BFMs and transactors, and delivering customer-ready solutions in a high‑impact R&D team. Familiarity with emulation platforms is a strong plus.