Senior Principal PCIe/CXL Verification Architect

Cadence; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Cadence in San Jose seeks an experienced engineer to advance PCIe/CXL AVIP and Virtual Bridge products. You will contribute to protocol functionality, performance, and robustness on emulation platforms. The role is hands-on, spanning hardware-software interfaces and regression activities.

You will design state machines, implement protocol features, enhance debug and analysis capabilities, and work with customers and field teams to deliver solutions related to PCIe and CXL.

Qualifications

• BS with strong fundamentals in digital design and system architecture.
• 10+ years (or equivalent) experience in verification on complex SoCs.
• Experience with SystemVerilog/Verilog and C/C++.
• Familiarity with PCIe, CXL, NVMe; emulation/acceleration flows a plus.

Responsibilities

• Design, develop, and maintain PCIe/CXL AVIP and Virtual Bridge components.
• Develop BFMs, transactors, and software interfaces for verification.
• Ensure correctness, performance, and scalability in emulation flows.
• Collaborate with cross-functional teams and support customer issues.

Skills

Digital design

Computer architecture

System-level verification

SystemVerilog/Verilog

C/C++

PCIe/CXL interconnects

Education

BS in Electrical Engineering / CS or related field

Tools

BFMs

Transactors

Emulation flows

Job description

Cadence in San Jose seeks an experienced engineer to advance PCIe/CXL AVIP and Virtual Bridge products. You will contribute to protocol functionality, performance, and robustness on emulation platforms. The role is hands-on, spanning hardware-software interfaces and regression activities.

You will design state machines, implement protocol features, enhance debug and analysis capabilities, and work with customers and field teams to deliver solutions related to PCIe and CXL.