Senior Principal Verification Engineer - Accelerated Verification IP

Cadence; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Cadence in San Jose seeks an experienced engineer to advance PCIe/CXL AVIP and Virtual Bridge products. You will contribute to protocol functionality, performance, and robustness on emulation platforms. The role is hands-on, spanning hardware-software interfaces and regression activities.

You will design state machines, implement protocol features, enhance debug and analysis capabilities, and work with customers and field teams to deliver solutions related to PCIe and CXL.

Qualifications

• BS with strong fundamentals in digital design and system architecture.
• 10+ years (or equivalent) experience in verification on complex SoCs.
• Experience with SystemVerilog/Verilog and C/C++.
• Familiarity with PCIe, CXL, NVMe; emulation/acceleration flows a plus.

Responsibilities

• Design, develop, and maintain PCIe/CXL AVIP and Virtual Bridge components.
• Develop BFMs, transactors, and software interfaces for verification.
• Ensure correctness, performance, and scalability in emulation flows.
• Collaborate with cross-functional teams and support customer issues.

Skills

Digital design

Computer architecture

System-level verification

SystemVerilog/Verilog

C/C++

PCIe/CXL interconnects

Education

BS in Electrical Engineering / CS or related field

Tools

BFMs

Transactors

Emulation flows

Job description

The AVIP (Accelerated Verification IP) and Virtual Bridge (VB) business is a core part of Cadence’s Virtual Emulation and System Verification portfolio, enabling high‑performance verification on Palladium and Protium platforms. The team builds high‑performance protocol solutions that enable customers to verify complex SoCs and systems at much higher speed and scale than traditional simulation.

Together, AVIP and VB are critical to customers building high‑performance compute, AI, networking, and memory‑coherent systems, where early software bring‑up, performance analysis, and protocol compliance are essential.

The AVIP / Virtual Bridge R&D team designs, implements, and productizes protocol solutions that span hardware, software, and system‑level verification. The team works across multiple layers, including:

• Protocol architecture and feature definition
• High‑performance transactor and BFM development
• Hardware‑software co‑simulation and emulation flows
• Debug, logging, performance profiling, and compliance features
• Customer enablement, escalations, and interoperability validation

The team supports a broad portfolio of industry‑standard protocols, such as PCIe, CXL, Ethernet, USB, UCIe, and emerging interconnects, and works closely with emulation platform teams, controller/PHY teams, and customers.

This role will contribute directly to the development and enhancement of PCIe/CXL AVIP and/or PCIe/CXL Virtual Bridge products, focusing on protocol functionality, performance, and robustness. Depending on the specific protocol area, the work may involve:

• Implementing PCIe protocol features and state machines
• Enhancing performance and scalability on emulation platforms
• Developing debug, trace, and analysis capabilities
• Working with customers and field teams to resolve issues and deliver solutions related to PCIe and CXL

In this role, the engineer will be responsible for designing, developing, and maintaining PCIe/CXL AVIP/VB components as part of a larger protocol solution. The role is hands‑on and spans feature development, validation, and customer readiness.

Key responsibilities include:

• Designing and implementing protocol functionality in PCIe AVIP and/or Virtual Bridge components
• Developing and debugging BFMs, transactors, and associated software interfaces
• Ensuring correctness, performance, and scalability in emulation and acceleration flows
• Collaborating with cross‑functional teams
• Participating in feature bring‑up, regression, and release activities
• Supporting customer issues, reproducing problems, and delivering fixes

What you’ll need

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Strong fundamentals in digital design, computer architecture, and system‑level verification
• Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++Understanding of standard interconnect or IO protocols (e.g., PCIe, CXL, NVMe)
• Familiarity with emulation, acceleration, or hybrid verification flows is a strong plus
• Good debugging skills using waveforms, logs, and protocol analyzers
• Ability to work across hardware and software boundaries