Senior Design Verification Engineer – PCIe & SV/UVM Lead

Credo Semiconductor, Inc.; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

Credo Semiconductor, Inc. in California seeks a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through verification plans, scalable testbenches, SV/UVM sequences, debugging, and collaboration with RTL designers and firmware teams.

You will verify PCIe subsystems, develop reusable testbenches, write assertions, and drive coverage closure while contributing to DV workflows and firmware simulations.

Qualifications

• BS or MS in Electrical Engineering or related field.
• 7+ years of RTL and functional verification using SV/UVM.
• PCIe verification experience.
• Experience with gate-level simulation and firmware-based simulation.
• Proficiency in RTL design and computer architecture concepts.
• Strong debugging, problem-solving, and analytical skills.
• Effective collaborator in cross-functional teams.

Responsibilities

• Understand design intent and develop verification plans.
• Develop reusable SV-UVM testbenches and test sequences.
• Verify PCIe subsystems and interfaces (I2C/I3C/SMBus/CPU/UART/SPI) at block and subsystem levels.
• Write assertions, checkers, and coverage; close gaps.
• Build firmware-based simulations in C to model FW behavior.
• Reproduce silicon failures in simulation and debug to root cause.
• Automate flows with scripting (Python/Perl/Shell).
• Collaborate with AEs and FW on DV findings.

Skills

SV/UVM verification

RTL verification

PCIe verification

Debugging and problem solving

Cross-functional collaboration

Education

BS in Electrical Engineering

MS in Electrical/Computer Engineering

Tools

SV/UVM testbench development

Job description

Credo Semiconductor, Inc. in California seeks a Senior Design Verification Engineer to ensure the quality and performance of complex digital designs through verification plans, scalable testbenches, SV/UVM sequences, debugging, and collaboration with RTL designers and firmware teams.

You will verify PCIe subsystems, develop reusable testbenches, write assertions, and drive coverage closure while contributing to DV workflows and firmware simulations.