Senior Principal Mixed-Signal Verification Architect

Qorvo, Inc.; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Qorvo is seeking a Sr Principal Mixed Signal Verification Engineer in San Jose to lead verification for power-management ICs. You will develop metric-driven plans, create constrained-random tests, and build models to support TL simulations, collaborating closely with design and test teams to ensure first-pass silicon success.

The role requires 15+ years in AMS design/verification, strong UVM expertise, and deep knowledge of PMIC blocks (LDO, amplifiers, Bandgaps, DCDC, oscillators).

Qualifications

• Bachelor’s degree in electrical engineering with strong focus on mixed-signal circuit design and verification.
• 15+ years of AMS design or verification experience.
• Proficiency in UVM environments with test cases, coverage models, and global checkers.

Responsibilities

• Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
• Develop and execute metric-driven design verification plans based on IC functional, performance, and test specs, focusing on customer use-case.
• Develop constrained random tests and automated checkers within our UVM environment.
• Build RNM or VerilogAMS models to support TL simulation.
• Collaborate with design to resolve verification issues.
• Partner with internal design and test teams to ensure device first-pass testability.
• Continuously improve verification methodologies with industry best practices.
• Automate verification tasks where applicable.

Skills

UVM environments

AMS design & verification

Spice/Spectre

Co-simulation

Python scripting

Education

Bachelor’s degree in electrical engineering

Master’s degree preferred

Tools

SV-UDN/EENET modeling

GUI & command-line simulations

Job description

Qorvo is seeking a Sr Principal Mixed Signal Verification Engineer in San Jose to lead verification for power-management ICs. You will develop metric-driven plans, create constrained-random tests, and build models to support TL simulations, collaborating closely with design and test teams to ensure first-pass silicon success.

The role requires 15+ years in AMS design/verification, strong UVM expertise, and deep knowledge of PMIC blocks (LDO, amplifiers, Bandgaps, DCDC, oscillators).