Sr Principal Mixed Signal Verification Engineer - 10289

Peyton Resource Group; Richardson (TX); In loco; USD 180.000 - 240.000; Tempo pieno

Vantaggi offerti da questo lavoro

Travel up to 10% domestically or国际

Descrizione del lavoro

Peyton Resource Group in Richardson, TX seeks a Senior Principal Mixed-Signal Verification Engineer to lead top-level verification for mixed-signal and power-management ICs, ensuring functional accuracy, performance, and manufacturability across diverse applications.

You will develop metric-driven verification plans, constrained-random tests, and RNM/Verilog-AMS models, collaborating with design and test teams to debug issues and improve first-pass silicon.

Competenze

• Bachelor’s degree in Electrical Engineering or a related field.
• 15+ years of experience in analog/mixed-signal design verification or power-management IC development, or equivalent education and experience.
• Strong expertise in UVM, test development, functional coverage, and global checkers.
• In-depth knowledge of analog and power-management circuits, including LDOs, amplifiers, bandgaps, DC-DC regulators, oscillators, and asynchronous state machines.
• Experience with SPICE/Spectre, event-based simulators, mixed-signal co-simulation, and simulation and silicon debugging.
• Excellent analytical, problem-solving, communication, and collaboration skills.

Mansioni

• Develop and execute metric-driven verification plans based on functional, performance, and test specifications.
• Create constrained-random tests, automated checkers, and coverage models within UVM environments.
• Develop accurate RNM and Verilog-AMS models for top-level simulations.
• Verify power-management ICs, including motor drivers, battery management, DC-DC regulators, and power-loss protection.
• Collaborate with design and test teams to debug issues and improve first-pass silicon success.
• Automate verification processes and continuously improve methodologies.
• Support customer-facing technical discussions and use-case-driven verification.

Conoscenze

UVM

Test development

Functional coverage

Global checkers

SPICE/Spectre

Verilog-AMS

Python

SystemVerilog

Formazione

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Strumenti

SPICE/Spectre

Verilog-AMS

SystemVerilog

UVM

Descrizione del lavoro

Senior Principal Mixed-Signal Verification Engineer

Experience: Senior-level, 15+ years

Position Summary

Lead top-level design verification for mixed-signal and power-management ICs, ensuring functional accuracy, performance, and manufacturability across diverse applications.

Key Responsibilities

• Develop and execute metric-driven verification plans based on functional, performance, and test specifications.
• Create constrained-random tests, automated checkers, and coverage models within UVM environments.
• Develop accurate RNM and Verilog-AMS models for top-level simulations.
• Verify power-management ICs, including motor drivers, battery management, DC-DC regulators, and power-loss protection.
• Collaborate with design and test teams to debug issues and improve first-pass silicon success.
• Automate verification processes and continuously improve methodologies.
• Support customer-facing technical discussions and use-case-driven verification.

Required Qualifications

• Bachelor’s degree in Electrical Engineering or a related field.
• 15+ years of experience in analog/mixed-signal design verification or power-management IC development, or equivalent education and experience.
• Strong expertise in UVM, test development, functional coverage, and global checkers.
• In-depth knowledge of analog and power-management circuits, including LDOs, amplifiers, bandgaps, DC-DC regulators, oscillators, and asynchronous state machines.
• Experience with SPICE/Spectre, event-based simulators, mixed-signal co-simulation, and simulation and silicon debugging.
• Excellent analytical, problem-solving, communication, and collaboration skills.

Preferred Qualifications

• Master’s degree in Electrical Engineering or a related field.
• Experience with top-down design and verification methodologies.
• Proficiency in Python or shell scripting.
• Familiarity with SV-UDN/EENET modeling, SystemVerilog assertions, and functional coverage.
• Experience with GUI-based and command-line simulation workflows.
• Understanding of AI integration into verification workflows.

Travel: Up to 10% domestic or international travel.