Senior Principal Analog Power IC Design Engineer

Qorvo, Inc.; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Qorvo is seeking a Senior Principal Analog Design Engineer in San Jose, CA to drive the architecture, design and validation of advanced analog power management ICs. You will lead transistor-level design, collaborate with system engineers, and work with global teams to achieve best-in-class efficiency and performance.

Responsibilities include defining architectures, selecting topologies, and coordinating with layout and test teams to ensure robust, manufacturable devices.

Qualifications

• Bachelor's degree in electrical engineering required.
• Minimum 15 years of engineering experience in semiconductors.
• 8+ years in analog/mixed-signal IC design with DC-DC power converters.
• Ability to communicate highly technical concepts to stakeholders.
• Experience with production release of PMICs.

Responsibilities

• Lead the design and development of high-performance analog PMICs.
• Collaborate with system engineers to define architecture and specs.
• Select and implement optimal circuit topologies for robustness and manufacturability.
• Conduct transistor-level design, simulation and validation.
• Work with layout engineers to optimize floor planning and silicon performance.
• Engage with global design teams to align strategies.
• Partner with test/validation teams to define methodologies and optimize production test.
• Drive technical reviews and present trade-offs to stakeholders.

Skills

Analog IC design

Power management

DC-DC architectures

Transistor-level simulation

EDA tools

Education

Bachelor's degree in Electrical Engineering

Master's or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Simplis

ADS

Job description

Qorvo is seeking a Senior Principal Analog Design Engineer in San Jose, CA to drive the architecture, design and validation of advanced analog power management ICs. You will lead transistor-level design, collaborate with system engineers, and work with global teams to achieve best-in-class efficiency and performance.

Responsibilities include defining architectures, selecting topologies, and coordinating with layout and test teams to ensure robust, manufacturable devices.