Sr Principal Mixed Signal Verification Engineer

Qorvo, Inc.; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Qorvo is seeking a Sr Principal Mixed Signal Verification Engineer in San Jose to lead verification for power-management ICs. You will develop metric-driven plans, create constrained-random tests, and build models to support TL simulations, collaborating closely with design and test teams to ensure first-pass silicon success.

The role requires 15+ years in AMS design/verification, strong UVM expertise, and deep knowledge of PMIC blocks (LDO, amplifiers, Bandgaps, DCDC, oscillators).

Qualifications

• Bachelor’s degree in electrical engineering with strong focus on mixed-signal circuit design and verification.
• 15+ years of AMS design or verification experience.
• Proficiency in UVM environments with test cases, coverage models, and global checkers.

Responsibilities

• Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
• Develop and execute metric-driven design verification plans based on IC functional, performance, and test specs, focusing on customer use-case.
• Develop constrained random tests and automated checkers within our UVM environment.
• Build RNM or VerilogAMS models to support TL simulation.
• Collaborate with design to resolve verification issues.
• Partner with internal design and test teams to ensure device first-pass testability.
• Continuously improve verification methodologies with industry best practices.
• Automate verification tasks where applicable.

Skills

UVM environments

AMS design & verification

Spice/Spectre

Co-simulation

Python scripting

Education

Bachelor’s degree in electrical engineering

Master’s degree preferred

Tools

SV-UDN/EENET modeling

GUI & command-line simulations

Job description

Sr Principal Mixed Signal Verification Engineer

Experience Level: Professional

Job Type: Regular

Location: San Jose, CA, US, 95134 Richardson, TX, US, 75081

Requisition ID: 10289

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.

Qorvo’s fast-growing Power Management division, focused on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IOT and Industrial applications, is looking for an experienced Top-level Design Verification Engineer to create next generation and world-class designs in power management solutions.

Responsibilities

• Serve as customer-facing for catalog and custom power-management ICs including motor driver, power-loss protection, point of load, and battery management IC solutions.
• Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use-case.
• Develop constrained random tests and automated checkers within our TLDV UVM environment.
• Build high performance, accurate RNM, or VerilogAMS models to support TL simulation.
• Collaborate with design team to resolve issues identified during verification.
• Partner with internal design and test teams to ensure device first-pass testability.
• Continuously improve and align verification methodologies with industry best practices
• Automate verification tasks where applicable.

Required Qualifications

• Bachelor’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
• 15+ years of experience or an equivalent amount of advanced education and experience in AMS design or verification of analog and power-management ICs.
• Proficiency in UVM environments, including test cases, coverage models, and global checkers.
• In-depth knowledge of power-management building blocks such as LDO, Amplifiers, Bandgaps, DCDC regulators, Oscillators, and asynchronous state machines.
• Excellent problem-solving and debugging skills
• Effective communication and collaboration skills.
• Expertise in mixed-signal concepts such as Spice/Spectre and event-based simulator, co-simulation environment, simulation debug, silicon debug

Preferred Qualifications

• Master’s degree in electrical engineering or a related field, with strong focus on mixed-signal circuit design and verification.
• Experience in Top-Down Design Methodology.
• Proficiency in shell or Python scripting.
• Familiarity with SV-UDN/EENET modeling techniques.
• Experience with both GUI and command-line simulation flows.
• Proficiency with SV Assertions and Functional coverage.
• Understanding integration of AI into a verification workflow

10% or less domestic or international travel may be required

This role is available in our Richardson, TX and San Jose, CA locations.

MAKE A DIFFERENCE AT QORVO

We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets - we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.