Sr. Mixed Signal Design Verification Manager

Qorvo, Inc.; Richardson (TX); On-site; USD 130,000 - 180,000; Full time

Job summary

Qorvo, Inc. is seeking a Sr. Mixed Signal Design Verification Manager in Richardson, TX to manage a team and drive technical strategies for verification excellence in power management ICs. The ideal candidate will have significant experience in AMS design and management, ensuring first-pass testability and developing verification methodologies. A Bachelor’s in Electrical Engineering is required, along with strong problem-solving and communication skills.

This position offers an opportunity to work in a collaborative environment focused on innovative semiconductor solutions, with potential for domestic and international travel.

Qualifications

• 15+ years of experience in AMS design or verification of analog and power-management ICs.
• Experience managing or leading a team.
• Strong technical background with hands-on experience in UVM.

Responsibilities

• Manage and grow a team of verification engineers.
• Drive technical direction and strategy for verification excellence.
• Develop and execute design verification plans.

Skills

UVM

Mixed-signal circuit design

Problem-solving skills

Communication skills

Python scripting

Education

Bachelor’s degree in electrical engineering or related field

Master’s degree in electrical engineering or related field

Tools

Spice/Spectre

SV Assertions

Python

Job description

Sr. Mixed Signal Design Verification Manager

Experience Level: Management

Job Type: Regular

Location: Richardson, TX, US, 75081

Requisition ID: 10286

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems‑level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high‑growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery‑powered appliances, network infrastructure, healthcare and aerospace/defense.

Qorvo’s fast‑growing Power Management division, focused on Power loss protection, PMICs, Motor Control, and Battery Management solutions for a wide range of Mobile, Consumer, IoT and Industrial applications, is looking for an experienced Top‑level Design Verification Engineer to create next generation and world‑class designs in power management solutions.

Responsibilities

• Manage and grow a team of verification engineers with different levels of experience, from entry level to senior principal level.
• Drive technical direction and strategy for verification excellence.
• Serve as customer‑facing for catalog and custom power‑management ICs including motor driver, power‑loss protection, point of load, and battery management IC solutions.
• Develop and execute metric‑driven design verification plans based upon IC functional, performance, and test specifications, with a strong focus on the customer use‑case.
• Develop constrained random tests and automated checkers within our TLDV UVM environment.
• Build high performance, accurate RNM, or Verilog‑AMS models to support TL simulation.
• Collaborate with design team to resolve issues identified during verification.
• Partner with internal design and test teams to ensure device first‑pass testability.
• Continuously improve and align verification methodologies with industry best practices.
• Automate verification tasks where applicable.

Required Qualifications

• Bachelor’s degree in electrical engineering or a related field, with strong focus on mixed‑signal circuit design and verification.
• 15+ years of experience or an equivalent amount of advanced education and experience in AMS design or verification of analog and power‑management ICs.
• Experience managing or being a functional team lead.
• Strong technical background with hands‑on experience in UVM, analog and digital design fundamentals, and system level knowledge of power management ICs.
• Excellent problem‑solving and debugging skills
• Effective communication and collaboration skills.
• Expertise in mixed‑signal concepts such as Spice/Spectre and event‑based simulator, co‑simulation environment, simulation debug, silicon debug.

Preferred Qualifications

• Master’s degree in electrical engineering or a related field, with strong focus on mixed‑signal circuit design and verification.
• Experience in Top‑Down Design Methodology.
• Proficiency in shell or Python scripting.
• Familiarity with SV‑UDN/EENET modeling techniques.
• Experience with both GUI and command‑line simulation flows.
• Proficiency with SV Assertions and Functional coverage.
• Understanding integration of AI into a verification workflow.

Other: 10% or less domestic or international travel may be required.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.