Senior Principal I/O SoC Architect: TSN & USB4

Ampere; Santa Clara (CA); On-site; USD 226,000 - 339,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401K plan

Unlimited flextime

Paid holidays

Snacks & beverages

Job summary

Ampere, a semiconductor design company, seeks a Sr. Principal I/O SoC Architect in Santa Clara, CA. You will own the I/O subsystem architecture for next‑gen server-class SoCs, guiding high‑speed interfaces including Ethernet and USB3.x/USB4, and aligning IP selection across teams.

You will mentor engineers, author architecture specs, and drive data‑driven decisions to optimize interconnects, TSN functionality, and silicon validation for energy‑efficient AI compute.

Qualifications

• 8+ years of proven SoC design or architecture experience.
• Hands-on Ethernet IP experience with TSN standards (IEEE 1588, 802.1AS).
• Strong USB3.x/USB4 IP knowledge and integration experience.
• Solid understanding of I/O subsystems and interconnects (AXI/CHI), DMA, and memory.
• End-to-end IP lifecycle experience: selection, integration, silicon validation, debugging.
• Desirable: PCIe Gen4/5/6; MIPI; DisplayPort; LPDDR4/5, DDR4/5; SerDes PHY.

Responsibilities

• Architect the overall I/O subsystem strategy for data movement and on-chip interconnects.
• Drive multi-gigabit Ethernet IP and TSN functionality integration.
• Own USB ecosystem from IP selection to seamless integration across USB3.x/USB4.
• Evaluate and select third-party IP for high-speed protocols with data-driven analysis.
• Collaborate with SoC architects, verification, physical design, and software teams.
• Author and maintain detailed architecture specifications and documentation.
• Mentor junior engineers and serve as go-to expert for high-speed IO protocols.

Skills

SoC design/architecture

Ethernet IP integration

USB protocol stack

I/O interconnects (AXI/CHI)

SerDes & PHY

IP lifecycle (selection to validation)

Education

BS/MS/PhD in EE/CE/CS with related experience

Job description

Ampere, a semiconductor design company, seeks a Sr. Principal I/O SoC Architect in Santa Clara, CA. You will own the I/O subsystem architecture for next‑gen server-class SoCs, guiding high‑speed interfaces including Ethernet and USB3.x/USB4, and aligning IP selection across teams.

You will mentor engineers, author architecture specs, and drive data‑driven decisions to optimize interconnects, TSN functionality, and silicon validation for energy‑efficient AI compute.