Sr. Principal I/O SoC Architect

Ampere; Portland (OR); On-site; USD 225,500 - 338,500; Full time

Job summary

Ampere, a semiconductor design company, is seeking a Sr. Principal I/O SoC Architect to own the I/O subsystem for next-gen server-class SoCs.

You will define data movement, on-chip interconnects, and external interfaces, leading Ethernet/TSN and USB ecosystem integration, with cross-team collaboration and architecture documentation. We value 8+ years in SoC design, strong TSN and USB expertise, and the ability to mentor engineers while delivering silicon-ready IP and robust IP lifecycle

Qualifications

• BS degree in Electrical/Computer Engineering or CS with 12 years of related experience; or MS with 8 years; or PhD with 5 years.
• Experience delivering designs across Ethernet/USB and high-speed IO.
• Strong knowledge of on-chip interconnects (AXI/CHI), DMA, memory subsystems.

Responsibilities

• Architect overall I/O subsystem strategy for next-gen SoCs.
• Lead integration of multi-gigabit Ethernet IP with TSN.
• Own USB ecosystem designs across USB3.x/USB4.
• Evaluate third-party IP for high-speed protocols.
• Collaborate with SoC, verification, PD, and software teams.
• Author architecture specifications and docs.
• Mentor junior engineers on high-speed IO.

Skills

SoC architecture

I/O subsystems

Ethernet IP

TSN standards

USB 3.x/USB4

AXI/CHI

DMA engines

Memory interfaces

IP lifecycle

PCIe Gen4/5/6

Education

BS/CE/CS + 12y

Job description

Invent the future with us.Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.

As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.

About The Role

As a Sr. Principal I/O SoC Architect, you will strategically own and lead the I/O subsystem architecture for next-generation server-class SoCs—finalizing the next-generation Ampere I/O and interconnect architecture and guiding execution for one or more critical subsystems. As the technical authority for high-speed interfaces, with a focus on advanced Ethernet solutions, you will make incisive, data-driven decisions that align and optimize across interacting subsystems.

What You'll Achieve

• Architect the overall I/O subsystem, defining the strategy for data movement, on-chip interconnects, and external interfaces for next-generation SoCs.
• Drive the architecture and integration of multi-gigabit Ethernet IP, prioritizing Time-Sensitive Networking (TSN) functionality.
• Own the end-to-end solutions for the latest USB ecosystem, guiding IP selection and integration across USB 3.x/USB4.
• Evaluate and select third-party IP for high-speed protocols, performing detailed analysis and making data-driven recommendations.
• Collaborate closely with SoC architects, verification, physical design, and software teams to ensure the IO subsystem integrates successfully and meets system-level goals.
• Author and maintain detailed architecture specifications and documentation.
• Mentor junior engineers and serve as the go-to expert for high-speed IO protocols across the company.

About You

• 8+ years of proven SoC design or architecture experience, with a significant focus on I/O subsystems.
• Deep, hands-on experience architecting and integrating Ethernet IP, with proven expertise in Time-Sensitive Networking (TSN) standards (e.g. IEEE 1588 and 802.1AS) and applications.
• Strong track record delivering designs using the USB protocol stack across USB3.x and USB4, addressing complex high-speed interoperability and integration issues.
• Solid understanding for I/O SoC architecture fundamentals, including on-chip interconnects (e.g., AXI/CHI), DMA engines, and memory subsystems,
• Experience across the full IP lifecycle, from selection and integration to silicon validation and debug.
• Additional skills highly desired: PCIe (Gen4/5/6); MIPI (C-PHY/D-PHY), DisplayPort; High-speed Memory Interfaces (LPDDR4/5, DDR4/5); SerDes PHY Integration; SI/PI

Education

• BS degree in Electrical Engineering, Computer Engineering, or Computer Science & 12 years of related experience, MS degree & 8 years, or PhD & 5 years

What We'll Offer

At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits. The full base pay range for this role is between $225,500 and $338,500, except in the San Francisco Bay Area where the range is between $237,000 and $356,000.

Our benefits include health, wellness, and financial programs that support employees through every stage of life.

Benefits Highlights Include

• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there are much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.