SoC DFT Test Architect (ATPG/MBIST) – Onsite Austin

Mogi I/O : OTT/Podcast/Short Video Apps for you; Austin (TX); On-site; USD 170,000 - 200,000; Full time

Job summary

A well-funded hardware startup in Austin is seeking an experienced DFT Engineer to innovate and own design-for-test methodologies for advanced digital and mixed-signal SoCs. Candidates should have 5-8 years of relevant experience and a master's degree in Electrical Engineering. This full-time role focuses on cross-functional collaboration to deploy robust DFT strategies for next-generation programmable DSP chips, targeting the fastest AI and cloud infrastructures.

Qualifications

• 5+ years in DFT spec, architecture, insertion, and analysis for complex silicon.
• Experience in silicon bring-up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG.
• ASIC DFT, synthesis, simulation/verification know-how.
• Strong organizational/problem-solving skills; detail oriented.
• Willing to work on-site in Austin, TX (Relocation not covered).

Responsibilities

• Lead and implement SoC DFT architecture and ATPG/MBIST strategy.
• Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST.
• Own silicon bring-up and ATE debug for new test features and DFT IP.
• Collaborate to improve test coverage, resolve RTL violations, and streamline test processes.
• Develop and maintain formal DFT documentation.

Skills

DFT Specification & Architecture

ATPG, MBIST, JTAG

Silicon Bring-up & Test (ATE)

Scan Chains, DFT Compression, Logic BIST

EDA Test Tools

IP Integration, ASIC Synthesis & Verification

Problem-Solving

Communication

Education

Master’s degree in Electrical Engineering

Tools

DFT Max

Tessent

Modus

Design/Fusion Compiler

SpyGlass

TestKompress

Job description

A well-funded hardware startup in Austin is seeking an experienced DFT Engineer to innovate and own design-for-test methodologies for advanced digital and mixed-signal SoCs. Candidates should have 5-8 years of relevant experience and a master's degree in Electrical Engineering. This full-time role focuses on cross-functional collaboration to deploy robust DFT strategies for next-generation programmable DSP chips, targeting the fastest AI and cloud infrastructures.