DFT Design Engineer

Cadence Design Systems; Austin (TX); On-site; USD 90,000 - 120,000; Full time

Job summary

Cadence Design Systems is seeking a DFT Design Engineer in Austin, Texas, to engage in digital design focusing on Design for Test (DFT). Applicants must have 2-10 years of relevant experience and be proficient in scan chain insertion, MBIST, and automatic test pattern generation (ATPG).

This role demands collaboration across various teams, problem-solving skills, and the ability to thrive in a fast-paced environment. Knowledge of Cadence tools is a plus, along with a systematic approach to quality metrics-driven work.

Qualifications

• 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT).
• Knowledge of memory built-in self-test (MBIST) and JTAG standards.
• Ability to debug and analyze failures to improve fault coverage.

Responsibilities

• Generate ATPG patterns to achieve design test coverage goals.
• Independently complete DFT tasks while collaborating with cross-functional teams.
• Develop debug and analysis of failures in the testbenches.

Skills

DFT insertion flows

Scan chain insertion

Automatic Test Pattern Generation (ATPG)

Debugging Verilog testbenches

Collaboration in team environment

Tools

Cadence tools

Job description

## DFT Design EngineerApplylocations: AUSTINtime type: Full timeposted on: Posted Todayjob requisition id: R55131## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**US citizenship RequiredWe are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.Requirements;* Prior 2-10 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)* Should possess intimate knowledge of DFT insertion flows* Basic scan chain insertion using synthesis or other software tools* Experience in compression scan insertion, LBIST and other scan technologies* Intimate knowledge of memory build-in self-test (MBIST)* Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals* Debug and Analysis of failures to improve fault coverage* Verification of ATPG testbenches and debugging root cause of simulation mis-compares* Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687* Knowledge of timing analysis and equivalency checks would be added bonus* US citizenship Required* Ability to work in collaborative team environment* Prior experience with Cadence tools and flows is highly desirable* Should be able to finish DFT tasks independently* Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems* Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers* Self-driven and committed individual who can work in a fast-paced project environment