Senior Principal Power Integrity & Signoff Architect

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Job summary

Cadence Design Systems, Inc. in San Jose seeks a Senior Principal Product Engineer to lead Voltus power integrity and reliability analysis efforts. You will bridge R&D, Applications, and customers to turn complex IR/EM and PDN signoff requirements into practical product flows.

You will mentor teams, define flows with foundries, influence the product roadmap including AI-driven IR mitigation and 3DIC capabilities, and present findings to leadership across geographies.

Qualifications

• Bachelor’s in Electrical / Electronics / VLSI Engineering with 10+ years of related experience, or MS with 8+ years, or PhD with 6+ years.
• Deep hands-on experience with industry-standard IR/EM (EMIR) and PDN analysis tools and digital physical implementation / signoff flows.
• Strong background in CMOS/digital design, power IR-drop analysis, circuit analysis, and low-power / multi-power-domain chip power-integrity signoff.
• Proven ability to debug large SoC/PDN problems and translate customer requirements to R&D fixes.
• Scripting in Tcl and Python; strong written, verbal, and presentation skills with customer and executive audiences.

Responsibilities

• Serve as the primary technical interface to R&D for Voltus, driving product requirements, priorities, and methodology for strategic foundry and customer programs.
• Lead Voltus enablement for advanced-node IR/EM signoff: flow/techfile/PDK readiness, reference flows, qualification, benchmarking, and production deployment.
• Own resolution of complex customer issues spanning static/dynamic IR, EM, low-power / multi-voltage domains, hierarchical and full-chip signoff, and related timing/stack-die interactions.
• Define and validate foundry-aligned power integrity and EM modeling assumptions; partner with PDK, extraction, and signoff teams on advanced-node and 3DIC readiness.
• Influence product roadmap (including AI-driven IR mitigation, 3DIC, and electrothermal co-analysis) based on foundry and customer gaps.
• Mentor Lead/Principal PEs and AEs; set debug standards, deployment practices, and issue-tracking discipline for the account/foundry program.
• Work effectively with customers, Cadence field, Marketing, and R&D across geographies; present findings and recommendations to customer and internal leadership.

Skills

IR/EM analysis

CMOS/digital design

Power integrity signoff

Scripting (Tcl, Python)

Education

Bachelor’s in Electrical / Electronics / VLSI Engineering

MS in Electrical / VLSI Engineering

PhD in Electrical / VLSI Engineering

Tools

Voltus

Integrity

Tempus

Innovus

Quantus/QRC

Job description

Cadence Design Systems, Inc. in San Jose seeks a Senior Principal Product Engineer to lead Voltus power integrity and reliability analysis efforts. You will bridge R&D, Applications, and customers to turn complex IR/EM and PDN signoff requirements into practical product flows.

You will mentor teams, define flows with foundries, influence the product roadmap including AI-driven IR mitigation and 3DIC capabilities, and present findings to leadership across geographies.